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m m m m m pd780228 subseries 8-bit single-chip microcontroller document no. u12012ej2v0um00 (2nd edition) date published june 1997 n printed in japan m pd780226 m pd780228 m PD78F0228 user? manual printed in japan 1997
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notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. fip and iebus are trademarks of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. ibm dos, pc/at, and pc dos are trademarks of ibm corporation. hp9000 series 300, hp9000 series 700, and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation. osf/motif is a trademark of open software foundation, inc. tron is an abbreviation of the real-time operating system nucleus. itron is an abbreviation of industrial tron.
license not needed: PD78F0228gf-3ba the customer must judge the need for license: m pd780226gf- -3ba, 780228gf- -3ba the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the information in this document is subject to change without notice. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m7 96.5
major revisions in this edition page description throughout change of m pd780226 and 780228 from under development to developed p.16 2.3 i/o circuits of pins and connections of unused pins change of i/o circuit types of ports 7, 8, 9, and 10 of mask rom model as follows: ports 7, 8, and 9: type 15-d to type 15-f port 10 : type 14-d to type 14-f p.33, 173, 175, 177 addition of internal expansion ram size select register (ixs) p.59-62 correction of block diagrams of ports 7, 8, 9, and 10 p.71 5.4.1 main system clock oscillator change of notes on inputting external clock p.78 change of count clock value by setting of tcl2 and tcl1 in figure 6-2 timer mode control register 1 format p.103, 164 change of oscillation stabilization time by setting of osts2-osts0 in format of oscillation stabilization time select register p.130 figure 11-2 display mode register 0 format change of setting of fout5-fout0, and addition of notes on fip output pins p.139 addition of 11.7 calculation of total power dissipation p.173, 175, 202 change of product name of dedicated flash writer as follows: flashpro to falshpro ii (part no.: fl-pr2) p.197 addition of appendix a differences between m m m m m pd78044h, 780228, and 780208 subseries p.203 change of hardware for debugging tools as follows: change of ie-780000-sl to ie-78001-r-a deletion of ie-78k0-sl-em (cpu core board) change of ep-100gf-sl from under development to developed previous edition deletion of upgrading your in-circuit emulator to emulator for 78k/0 series p.217 addition of appendix e revision history the mark shows major revised points.
nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
preface readers this manual has been prepared for user engineers who understand the functions of the m pd780228 subseries and design and develop its application systems and programs. purpose this manual is intended for the users to understand the functions described in the organization section below. organization the m pd780228 subseries manual is separated into two parts: this manual and instructions (common to the 78k/0 series) m pd780228 subseries 78k/0 series users manual users manual (this manual) instructions ? pin functions ? cpu functions ? internal block functions ? instruction set ? interrupts ? explanation of each instruction ? miscellaneous on-chip peripheral functions how to read this manual before reading this manual, you must have general knowledge of electric and logic circuits and microcomputer. when you want to understand the functions in general: ? read this manual in the order of the contents. how to interpret the register format: ? for the circled bit number, the bit name is defined as a reserved word in ra78k/0, and in cc78k/0, already defined in the header file named sfrbit.h. when confirming the details of the register whose register name is known: ? refer to appendix d register index . when you want to know the differences between the m pd78044h subseries and the m pd780208 subseries: ? refer to appendix a differences between m m m m m pd78044h, 780228, and 780208 subseries . when you want to know the details of the m pd780228 subseries instruction funcion: ? refer to 78k/0 series users manual: instruction. (u12326e) . when you want to know the electrical characteristics of the m pd780288 subseries: ? refer to m m m m m pd780226 , 780228 data sheet (u11797e) separately available. when you want to know the application examples of each function of the m pd780228 subseries ? refer to 78k/0 series application note - fundamental (ii) (u10121e) separately available.
legend data representation weight : high digits on the left and low digits on the right active low representations : xxx (top bar over pin or signal name) note : description of note in the text. caution : information requiring particular attention remark : additional explanatory material numeral representations : binary .............. xxxx or xxxxb decimal ........... xxxx hexadecimal ... xxxxh related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. ? documents related to devices document name document number english japanese m pd780228 subseries users manual this manual u12012j m pd780226, 780228 data sheet u11797e u11797j m PD78F0228 preliminary product information u11971e u11971j 78k/0 series instruction table u10903j 78k/0 series instruction set u10904j 78k/0 series users manual: instructions u12326e u12326j 78k/0 series application note: fundamental (ii) u10121e u10121j caution the contents of the above documents are subject to change without notice. be sure to use the latest edition for designing.
? documents related to development tools (users manual) document name document number english japanese ra78k series assembler package operation eeu-1399 eeu-809 language eeu-1404 eeu-815 ra78k series structured assembler preprocessor eeu-1402 eeu-817 ra78k0 assembler package operation u11802e u11802j assembly language u11801e u11801j structured assembly u11789e u11789j language cc78k series c compiler operation eeu-1280 eeu-656 language eeu-1284 eeu-655 cc78k0 c compiler operation u11517e u11517j language u11518e u11518j cc78k series library source file u12322j cc78k compiler application note programming know-how eea-1208 eea-618 ie-78001-r-a planned planned ie-78k0-sl-p01 planned planned ie-780228-sl-em4 planned planned ep-100gf-sl planned planned sm78k0 system simulator windows tm base reference u10181e u10181j sm78k series system simulator external components user u10092e u10092j open interface specifications id78k0 integrated debugger ews base reference u11151j id78k0 integrated debugger pc base reference u11539e u11539j id78k0 integrated debugger windows base guide u11649e u11649j caution the contents of the above documents are subject to change without notice. be sure to use the latest edition for designing.
? documents related to embedded software (users manual) document name document number english japanese 78k/0 series real-time os fundamental u11537j installation u11536j 78k/0 series os mx78k0 fundamental u12257j fuzzy knowledge data creation tool eeu-1438 eeu-829 78k/0, 78k/ii, 87ad series fuzzy inference development support system translator eeu-1444 eeu-862 78k/0 series fuzzy inference development support system fuzzy inference module eeu-1441 eeu-858 78k/0 series fuzzy inference development support system fuzzy inference debugger eeu-1458 eeu-921 ? other related documents document name document number english japanese ic package manual c10943x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor devices c11531e c11531j nec semiconductor device reliability/quality control system c10983e c10983j electrostatic discharge (esd) test mem-539 guide to quality assurance for semiconductor devices mei-1202 c11893j microcomputer product guide Cby third party u11416j caution the contents of the above documents are subject to change without notice. be sure to use the latest edition for designing.
C i C table of contents chapter 1 general .......................................................................................................................... 1 1.1 features .................................................................................................................................. 1 1.2 application fields ................................................................................................................. 1 1.3 ordering information ............................................................................................................ 1 1.4 pin configuration (top view) ............................................................................................... 2 1.5 78k/0 series expansion ....................................................................................................... 4 1.6 block dia gram ....................................................................................................................... 6 1.7 functional outline ................................................................................................................. 7 1.8 mask option ........................................................................................................................... 8 chapter 2 pin functions ................................................................................................................ 9 2.1 pin function list ................................................................................................................... 9 2.2 pin functions ....................................................................................................................... 12 2.2.1 p00 and p01 (port 0) ................................................................................................................ 12 2.2.2 p10 through p17 (port 1) .......................................................................................................... 12 2.2.3 p20 through p25 (port 2) .......................................................................................................... 12 2.2.4 p40 through p47 (port 4) .......................................................................................................... 13 2.2.5 p50 through p57 (port 5) .......................................................................................................... 13 2.2.6 p60 through p67 (port 6) .......................................................................................................... 13 2.2.7 p70 through p77 (port 7) .......................................................................................................... 13 2.2.8 p80 through p87 (port 8) .......................................................................................................... 13 2.2.9 p90 through p97 (port 9) .......................................................................................................... 14 2.2.10 p100 through p107 (port 10) .................................................................................................... 14 2.2.11 fip0 through fip15 ................................................................................................................... 14 2.2.12 v load .......................................................................................................................................... 14 2.2.13 av dd ........................................................................................................................................... 14 2.2.14 av ss ............................................................................................................................................ 14 2.2.15 reset ....................................................................................................................................... 14 2.2.16 x1 and x2 .................................................................................................................................. 14 2.2.17 v dd0 through v dd2 ...................................................................................................................... 15 2.2.18 v ss0 and v ss1 ............................................................................................................................. 15 2.2.19 v pp ( m PD78F0228 only) ............................................................................................................ 15 2.2.20 ic (mask rom productonly) ..................................................................................................... 15 2.3 i/o circuits of pins and connections of unused pins ................................................... 16 chapter 3 cpu architecture ..................................................................................................... 19 3.1 memory space ..................................................................................................................... 19 3.1.1 internal program memory space ............................................................................................... 22 3.1.2 internal data memory space ..................................................................................................... 23 3.1.3 special function register (sfr) area ........................................................................................ 23 3.1.4 data memory addressing .......................................................................................................... 24
C ii C 3.2 processor registers ........................................................................................................... 28 3.2.1 control registers ........................................................................................................................ 28 3.2.2 general registers ....................................................................................................................... 31 3.2.3 special function registers (sfr: special function register) ................................................. 32 3.3 addressing of instruction address .................................................................................. 35 3.3.1 relative addressing ................................................................................................................... 35 3.3.2 immediate addressing ............................................................................................................... 36 3.3.3 table indirect addressing .......................................................................................................... 37 3.3.4 register addressing .................................................................................................................. 38 3.4 addressing of operand address ...................................................................................... 39 3.4.1 implied addressing .................................................................................................................... 39 3.4.2 register addressing .................................................................................................................. 40 3.4.3 direct addressing ....................................................................................................................... 41 3.4.4 short direct addressing ............................................................................................................. 42 3.4.5 special function register (sfr) addressing ............................................................................. 44 3.4.6 register indirect addressing ..................................................................................................... 45 3.4.7 based addressing ...................................................................................................................... 46 3.4.8 based indexed addressing ........................................................................................................ 47 3.4.9 stack addressing ....................................................................................................................... 47 chapter 4 port functions ......................................................................................................... 49 4.1 port functions ..................................................................................................................... 49 4.2 port configuration ............................................................................................................... 51 4.2.1 port 0 .......................................................................................................................................... 51 4.2.2 port 1 .......................................................................................................................................... 53 4.2.3 port 2 .......................................................................................................................................... 54 4.2.4 port 4 .......................................................................................................................................... 56 4.2.5 port 5 .......................................................................................................................................... 57 4.2.6 port 6 .......................................................................................................................................... 58 4.2.7 port 7 .......................................................................................................................................... 59 4.2.8 port 8 .......................................................................................................................................... 60 4.2.9 port 9 .......................................................................................................................................... 61 4.2.10 port 10 ........................................................................................................................................ 62 4.3 port function control registers ....................................................................................... 63 4.4 port function operations ................................................................................................... 66 4.4.1 writing to input/output port ....................................................................................................... 66 4.4.2 reading from input/output port ................................................................................................. 66 4.4.3 operations on input/output port ................................................................................................ 66 4.5 selecting mask option ....................................................................................................... 67 chapter 5 clock generator .................................................................................................... 69 5.1 clock generator functions ................................................................................................ 69 5.2 clock generator configuration ......................................................................................... 69 5.3 register controlling clock generation circuit ............................................................... 70 5.4 system clock oscillator ..................................................................................................... 71 5.4.1 main system clock oscillator ..................................................................................................... 71 5.4.2 divider ........................................................................................................................................ 73
C iii C 5.5 clock generator operations .............................................................................................. 74 5.6 changing cpu clock .......................................................................................................... 75 5.6.1 time required to change cpu clock ......................................................................................... 75 5.6.2 cpu clock changing procedure ................................................................................................ 76 chapter 6 8-bit remote control timer ................................................................................. 77 6.1 function of 8-bit remote control timer .......................................................................... 77 6.2 configuration of 8-bit remote control timer .................................................................. 77 6.3 registers controlling 8-bit remote control timer ......................................................... 78 6.4 operation of 8-bit remote control timer ........................................................................ 80 chapter 7 8-bit pwm timers ........................................................................................................ 83 7.1 functions of 8-bit pwm timers ......................................................................................... 83 7.2 configuration of 8-bit pwm timers .................................................................................. 84 7.3 registers controlling 8-bit pwm timers .......................................................................... 86 7.4 operations of 8-bit pwm timers ....................................................................................... 89 7.4.1 operation as interval timer (8-bit operation) ............................................................................ 89 7.4.2 operation as exter nal event counter ........................................................................................ 92 7.4.3 square wave (8-bit resolution) output operation ...................................................................... 93 7.4.4 8-bit pwm output operation ...................................................................................................... 94 7.5 notes on 8-bit pwm timers ............................................................................................... 99 chapter 8 watchdog timer ....................................................................................................... 101 8.1 function of watc hdog timer ............................................................................................ 101 8.2 configuration of watc hdog timer ................................................................................... 102 8.3 registers controlling watc hdog timer ........................................................................... 103 8.4 operation of watc hdog timer .......................................................................................... 106 8.4.1 oper ation as watchdog timer .................................................................................................. 106 8.4.2 operation as interval timer ...................................................................................................... 107 chapter 9 a/d conve rter .......................................................................................................... 109 9.1 function of a/d co nverter ............................................................................................... 109 9.2 configuration of a/d co nverter ...................................................................................... 109 9.3 registers controlling a/d co nverter .............................................................................. 112 9.4 operation of a/d co nverter ............................................................................................. 114 9.4.1 basic operation of a/d converter ............................................................................................ 114 9.4.2 input voltage and conversion result ........................................................................................ 116 9.4.3 operation mode of a/d converter ........................................................................................... 117 9.5 notes on a/d converter ................................................................................................... 118 chapter 10 serial interface ................................................................................................... 121 10.1 function of serial interface ............................................................................................. 121 10.2 configuration of serial interface ..................................................................................... 121 10.3 registers controlling serial interface ............................................................................ 123 10.4 operation of serial interface ........................................................................................... 124 10.4.1 operation stop mode ............................................................................................................... 124 10.4.2 three-wire serial i/o mode ..................................................................................................... 125
C iv C chapter 11 fip controller/driver ....................................................................................... 127 11.1 function of fip controller/driver .................................................................................... 127 11.2 configuration of fip controller/driver ........................................................................... 128 11.3 registers controlling fip controller/driver ................................................................... 129 11.3.1 control registers ...................................................................................................................... 129 11.3.2 one display period and blanking width .................................................................................. 133 11.4 display data memory ........................................................................................................ 134 11.5 key scan flag and key scan data .................................................................................. 135 11.5.1 key scan flag ........................................................................................................................... 135 11.5.2 key scan data .......................................................................................................................... 135 11.6 leakage emission of fluorescent indicator p anel ....................................................... 136 11.7 calculation of total power dissipation .......................................................................... 139 chapter 12 interrupt functions .......................................................................................... 143 12.1 interrupt function types .................................................................................................. 143 12.2 interrupt sources and configuration ............................................................................. 145 12.3 interrupt function control registers ............................................................................. 148 12.4 interrupt servicing operations ........................................................................................ 153 12.4.1 non-maskable interrupt request acknowledge operation ...................................................... 153 12.4.2 maskable interrupt request acknowledge operation .............................................................. 156 12.4.3 software interrupt request acknowledge operation ............................................................... 158 12.4.4 multiple interrupt servicing ...................................................................................................... 159 12.4.5 interrupt request reserve ......................................................................................................... 162 chapter 13 standby function ................................................................................................ 163 13.1 standby function and configuration ............................................................................. 163 13.1.1 standby function ...................................................................................................................... 163 13.1.2 standby function control register ............................................................................................ 164 13.2 standby function operations .......................................................................................... 165 13.2.1 halt mode .............................................................................................................................. 165 13.2.2 stop mode ............................................................................................................................. 168 chapter 14 reset function ..................................................................................................... 171 14.1 reset function .................................................................................................................. 171 chapter 15 m m m m m PD78F0228 ................................................................................................................ 175 15.1 memory size select register ........................................................................................... 176 15.2 internal expansion ram size select register .............................................................. 177 15.3 flash memory programming ........................................................................................... 173 15.3.1 selecting communication mode .............................................................................................. 173 15.3.2 function of flash memory programming ................................................................................. 179 15.3.3 connection of flashpro ii ........................................................................................................ 180 chapter 16 instruction set .................................................................................................... 181 16.1 legend ................................................................................................................................ 182 16.1.1 operand identifiers and description methods ........................................................................ 182 16.1.2 description of operation column ........................................................................................... 183 16.1.3 description of flag operation column .................................................................................... 183
C v C 16.2 operation list .................................................................................................................... 185 16.3 instructions listed by addressing type ........................................................................ 192 appendix a differences between m m m m m pd78044h, 780228, and 780208 subseries ....... 197 appendix b development tools ............................................................................................ 199 b.1 language processing software ...................................................................................... 201 b.2 flash memory writing t ools ............................................................................................ 202 b.3 debugging t ools ................................................................................................................ 203 b.3.1 hardware .................................................................................................................................... 203 b.3.2 software ..................................................................................................................................... 204 b.4 os for ibm pc .................................................................................................................... 206 appendix c embedded software ........................................................................................... 211 c.1 real-time os ...................................................................................................................... 212 c.2 fuzzy inference development support system ............................................................ 214 appendix d register index ...................................................................................................... 215 d.1 register index .................................................................................................................... 215 appendix e revision history ................................................................................................... 217
C vi C list of figures (1/3) figure no. title page 2-1 pin input/output circuit list .................................................................................................................... 17 3-1 memory map ( m pd780226) ..................................................................................................................... 19 3-2 memory map ( m pd780228) ..................................................................................................................... 20 3-3 memory map ( m PD78F0228) ................................................................................................................... 21 3-4 addressing of data memory ( m pd780226) ............................................................................................ 25 3-5 addressing of data memory ( m pd780228) ............................................................................................ 26 3-6 addressing of data memory ( m PD78F0228) .......................................................................................... 27 3-7 program counter configuration .............................................................................................................. 28 3-8 program status word configuration ....................................................................................................... 28 3-9 stack p ointer configuration ..................................................................................................................... 29 3-10 ata to be saved to stack memory ........................................................................................................... 30 3-11 data to be restored from stack memory ............................................................................................... 30 3-12 general register configuration ............................................................................................................... 31 4-1 port types ................................................................................................................................................. 49 4-2 p00 and p01 block diagram ................................................................................................................... 52 4-3 p10 to p17 block diagram ...................................................................................................................... 53 4-4 p20 block diagram .................................................................................................................................. 54 4-5 p21 to p25 block diagram ...................................................................................................................... 55 4-6 p40 to p47 block diagram ...................................................................................................................... 56 4-7 p50 to p57 block diagram ...................................................................................................................... 57 4-8 p56 to p58 block diagram ...................................................................................................................... 58 4-9 p70 to p77 block diagram ...................................................................................................................... 59 4-10 p80 to p87 block diagram ...................................................................................................................... 60 4-11 p90 to p97 block diagram ...................................................................................................................... 61 4-12 p100 to p107 block diagram .................................................................................................................. 62 4-13 port mode register fo rmat ..................................................................................................................... 64 4-14 pull-up resistor option register format ............................................................................................... 65 5-1 block diagram of clock generation circuit ............................................................................................ 69 5-2 processor clock control register fo rmat .............................................................................................. 70 5-3 external circuit of main system clock oscillator ................................................................................... 71 5-4 examples of resonator with bad connection ........................................................................................ 72 5-5 changing cpu clock ............................................................................................................................... 76 6-1 block diagram of 8-bit remote control timer ....................................................................................... 77 6-2 timer mode control register 1 fo rmat .................................................................................................. 78 6-3 timing of pulse width measurement ...................................................................................................... 80 7-1 8-bit pwm timers block diagram ........................................................................................................... 84 7-2 format of timer clock select register ................................................................................................... 86 7-3 format of 8-bit timer control register 5n ............................................................................................. 88
C vii C 7-4 timing of interval timer operation ......................................................................................................... 90 7-5 timing of external event counter operation (with rising edge specified) ............................................ 92 7-6 pwm output operation timing ............................................................................................................... 95 7-7 oper ation timing when cr5n is changed ............................................................................................ 96 7-8 16-bit resolution cascade mode ............................................................................................................ 98 7-9 start timing of 8-bit counter 5n (tm5n) ................................................................................................ 99 7-10 timing after changing compare register v alue during timer count operation .................................. 99 8-1 watchdog timer block diagram ............................................................................................................ 102 8-2 oscillation stabilization time select register format ......................................................................... 103 8-3 watchdog timer clock select register format ................................................................................... 104 8-4 watchdog timer mode register format ............................................................................................... 105 9-1 a/d converter block diagram ............................................................................................................... 110 9-2 a/d converter mode register format .................................................................................................. 112 9-3 analog input channel specification register fo rmat .......................................................................... 113 9-4 basic operation of a/d converter ......................................................................................................... 115 9-5 relation between input analog voltage and a/d conversion result .................................................. 116 9-6 a/d conversion by software start ........................................................................................................ 117 9-7 example of reducing current consumption in standby mode ........................................................... 118 9-8 processing of analog input pin ............................................................................................................. 119 9-9 a/d conversion end interrupt request generation timing ................................................................. 120 9-10 processing of av dd pin .......................................................................................................................... 120 10-1 serial interface block diagram .............................................................................................................. 122 10-2 format of serial operation mode register 3 ....................................................................................... 123 10-3 timing in three-wire serial i/o mode .................................................................................................. 126 11-1 fip controller/driver block diagram ..................................................................................................... 128 11-2 display mode register 0 fo rmat ........................................................................................................... 130 11-3 display mode register 1 fo rmat ........................................................................................................... 131 11-4 display mode register format .............................................................................................................. 132 11-5 blanking width of fip output signal .................................................................................................... 133 11-6 relation between address location of display data memory and fip output (with 48 fip output pins and 16 patterns) ............................................................................................ 134 11-7 leakage emission because of short blanking time ........................................................................... 136 11-8 leakage emission caused by c sg ....................................................................................................... 137 11-9 leakage emission caused by c sg ....................................................................................................... 138 11-10 total power dissipation p t (t a = C40 to +85 c) .................................................................................. 139 11-11 relationship between display data memory and fip output with 10 segments-11 digits displayed ................................................................................................. 141 list of figures (2/3) figure no. title page
C viii C 12-1 basic configuration of interrupt function ............................................................................................. 145 12-2 interrupt request flag register format ............................................................................................... 148 12-3 interrupt mask flag register format .................................................................................................... 149 12-4 prior ity specify flag register fo rmat ................................................................................................... 150 12-5 external interrupt rising edge enable register fo rmat ...................................................................... 151 12-6 external interrupt f alling edge enable register format ..................................................................... 151 12-7 program status word configuration ..................................................................................................... 152 12-8 flowchart of occurrence and acknowledge non-maskable inter rupt ................................................. 154 12-9 non-maskable interrupt request acknowledge timing ....................................................................... 154 12-10 non-maskable interrupt request acknowledge operation .................................................................. 155 12-11 interrupt request acknowledge processing algorithm ........................................................................ 157 12-13 interrupt request acknowledge timing (maximum time) ................................................................... 158 12-12 interrupt request acknowledge timing (minimum time) .................................................................... 158 12-14 multiple interrupt examples ................................................................................................................... 160 12-15 interrupt request reserve .................................................................................................................... 162 13-1 oscillation stabilization time select register format ......................................................................... 164 13-2 halt mode clear upon interr upt request generation ........................................................................ 166 13-3 halt mode release by reset input .................................................................................................. 167 13-4 stop mode release by interrupt request generation ....................................................................... 169 13-5 release by stop mode reset input ................................................................................................. 170 14-1 block diagram of reset function .......................................................................................................... 171 14-2 timing of reset input by reset input ................................................................................................. 172 14-3 timing of reset due to watchdog timer ov erflow ............................................................................... 172 14-4 timing of reset in stop mode by reset input ................................................................................. 172 15-1 memory size select register format ................................................................................................... 172 15-2 internal expansion ram size select register format ........................................................................ 177 15-3 communication mode select format .................................................................................................... 178 15-4 connection of flashpro ii in 3-wire ser ial i/o mode ........................................................................... 180 15-5 connection of flashpro ii in pseudo 3-wire serial i/o mode ............................................................. 180 b-1 development tools ................................................................................................................................. 200 b-2 nqpack100rb (target-connected side) package drawings (refer nce) .......................................... 207 b-3 hqpack100rb (lid for device mounted) package drawings (reference) ........................................ 208 b-4 yqpack100rb (probe side) package drawings (reference) ............................................................ 209 list of figures (3/3) figure no. title page
C ix C list of tables (1/2) table no. title page 1-1 mask options of mask rom models ........................................................................................................ 8 2-1 i/o circuit type of each pin .................................................................................................................... 16 3-1 internal rom capacity ............................................................................................................................ 22 3-2 vector table .............................................................................................................................................. 22 3-3 special function registers ...................................................................................................................... 33 4-1 port function ............................................................................................................................................ 50 4-2 port configuration .................................................................................................................................... 51 4-3 port mode register and output latch setting when alternate function is used ................................ 63 4-4 comparison between mask options of mask rom models and m PD78F0228 .................................... 67 5-1 clock generator configuration ................................................................................................................ 69 5-2 relation between cpu clock and minimum instruction execution time .............................................. 70 5-3 maximum time required for changing cpu clock ............................................................................... 75 6-1 8-bit remote control timer configuration .............................................................................................. 77 7-1 configuration of 8-bit pwm timers ........................................................................................................ 84 8-1 hang-up detection time of watchdog timer ........................................................................................ 101 8-2 interval time ........................................................................................................................................... 101 8-3 configuration of watchdog timer .......................................................................................................... 102 8-4 hang-up detection time of watchdog timer ........................................................................................ 106 8-5 interval time of interval timer ............................................................................................................... 107 9-1 a/d converter configuration ................................................................................................................. 109 10-1 serial interface configuration ................................................................................................................ 121 11-1 fip output pins and multiplexed port pins .......................................................................................... 127 11-2 fip controller/driver configuration ....................................................................................................... 128 12-1 interrupt sources ................................................................................................................................... 144 12-2 various flags corresponding to interrupt request sources ............................................................... 147 12-3 times from maskable interrupt request generation to interrupt service .......................................... 156 12-4 interrupt request enab led for multiple interrupt during interrupt ser vicing ....................................... 159 13-1 halt mode operating status ................................................................................................................ 165 13-2 operation after halt mode release .................................................................................................... 167 13-3 stop mode oper ating status ............................................................................................................... 168 13-4 operation after stop mode release ................................................................................................... 170
C x C 14-1 hardw are status after reset ................................................................................................................. 173 15-1 differences between m PD78F0228 and mask rom models ............................................................... 175 15-2 set v alue of memory size select register ........................................................................................... 176 15-3 communication modes .......................................................................................................................... 178 15-4 major functions of flash memory programming ................................................................................. 179 16-1 operand identifiers and description methods ...................................................................................... 182 a-1 major differences between m pd78044h, 780228, and 780208 subseries ......................................... 197 list of tables (2/2) table no. title page
chapter 1 general 1 chapter 1 general 1.1 features ? high-capacity rom and ram item program memory data memory mask rom flash memory internal high- internal fip tm display part number speed ram expansion ram ram m pd780226 48k bytes 1024 bytes 512 bytes 96 bytes m pd780228 60k bytes m PD78F0228 60k bytes note note 48k or 60k bytes can be selected by the memory size select register (ims). ? minimum instruction execution time changeable from high speed (0.4 m s) to low speed (6.4 m s) ? i/o port : 72 pins ? fip controller/driver : total display output pins: 48 (universal grid compatible) ? display current 10 ma : 16 pins ? display current 3 ma : 32 pins ? 8-bit resolution a/d converter : 8 channels ? supply voltage (av dd = 4.5 to 5.5 v) ? serial interface : 1 channel ? 3-wire serial i/o mode : 1 channel ? timer: 4 channels ? 8-bit remote control timer : 1 channel ? 8-bit pwm timer : 2 channels ? watchdog timer : 1 channel ? vectored interrupt source : 12 ? supply voltage : v dd = 4.5 to 5.5 v 1.2 application fields combined mini-component audio systems, separate mini-component audio systems, tuners, cassette decks, cd players, and audio amplifiers 1.3 ordering information part number package internal rom m pd780226gf- -3ba 1 00-pin plastic qfp (14 20 mm) mask rom m pd780228gf- -3ba 1 00-pin plastic qfp (14 20 mm) mask rom m PD78F0228gf-3ba note 100-pin plastic qfp (14 20 mm) flash memory note under development remark indicates a rom code number.
chapter 1 general 2 1.4 pin configuration (top view) ? 100-pin plastic qfp (14 20 mm) m m m m m pd780226gf-xxx-3ba, 780228gf-xxx-3ba, 78f0228gf-3ba note 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p60 p61 p62 p63 p64 p65 p66 p67 p50 p51 p52 p53 p54 p55 p56 p57 ic(v pp ) v ss0 v dd0 p40 p41 p42 p43 p44 p45 p46 p47 p00/intp0 p01/intp1 reset fip0 fip1 fip2 fip3 fip4 fip5 fip6 fip7 fip8 fip9 fip10 fip11 fip12 fip13 fip14 fip15 p70/fip16 p71/fip17 p72/fip18 p73/fip19 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 v load v dd2 p74/fip20 p75/fip21 p76/fip22 p77/fip23 p80/fip24 p81/fip25 p82/fip26 p83/fip27 p84/fip28 p85/fip29 p86/fip30 p87/fip31 p90/fip32 p91/fip33 p92/fip34 p93/fip35 p94/fip36 p95/fip37 p96/fip38 p97/fip39 p100/fip40 p101/fip41 p102/fip42 p103/fip43 p104/fip44 p105/fip45 p106/fip46 p107/fip47 10099989796959493929190898887868584838281 p20/sck p21/so p22/si p23/ti1 p24/tio50 p25/tio51 v dd1 x2 x1 v ss1 av dd p10/ani0 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av ss 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 note under development cautions 1. directly connect the ic (internally connected) pin to v ss1 in the normal operation mode. 2. connect the av dd pin to v dd1 . 3. connect the av ss pin to v ss1 . remarks 1. when using the microcontroller in an application where the noise generated from the microcontroller must be suppressed, it is recommended that power be supplied to v dd0 and v dd1 from separate sources, and that v ss0 and v ss1 be connected to separate ground lines, to improve the noise immunity. 2. ( ): m PD78F0228
chapter 1 general 3 ani0-ani7 : analog input av dd : analog power supply av ss : analog ground fip0-fip47 : fluorescent indicator panel ic : internally connected intp0, intp1 : interrupt from peripherals p00, p01 : port0 p10-p17 : port1 p20-p25 : port2 p40-p47 : port4 p50-p57 : port5 p60-p67 : port6 p70-p77 : port7 p80-p87 : port8 p90-p97 : port9 p100-p107 : port10 reset : reset sck : serial clock si : serial input so : serial output ti1 : timer input tio50, tio51 : timer input/output v dd0 -v dd2 : power supply v load : negative power supply v pp : programming power supply v ss0 , v ss1 : ground x1, x2 : crystal
chapter 1 general 4 1.5 78k/0 series expansion the following shows the 78k/0 series products development. subseries name are shown inside frames. note under planning 64-pin 64-pin 64-pin 64-pin 80-pin 80-pin emi-noise reduced version of the pd78054 uart and d/a converter were enhanced to the pd78014 and i/o was enhanced pd78054 pd78054y pd78058f pd78058fy pd780034 pd780024 pd780964 pd780924 pd780034y pd780024y m m m m m m m m m m 64-pin a/d converter of the pd780024 was enhanced serial i/o of the pd78018f was added and emi-noise was reduced. on-chip inverter control circuit and uart. emi-noise was reduced. m m m m a/d converter of the pd780924 was enhanced m pd78044f pd78044h 80-pin 80-pin pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y pd78098 80-pin pd78p0914 64-pin 78k/0 series an n-ch open drain i/o was added to the pd78044f, display output total: 34 basic subseries for driving fip, display output total: 34 lcd drive the sio of the pd78064 was enhanced, and rom, ram capacity increased emi-noise reduced version of the pd78064 basic subseries for driving lcds, on-chip uart iebus tm supported an iebus controller was added to the pd78054 lv on-chip pwm output, lv digital code decoder, and hsync counter m m m m m m m m m m m m m m m m pd78083 pd78002 pd78002y pd780001 pd78014 pd78014y pd78018f pd78018fy low-voltage (1.8 v) operation version of the pd78014, with larger selection of rom and ram capacities an a/d converter and 16-bit timer were added to the pd78002 an a/d converter was added to the pd78002 basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) m m m m m m m m 42/44-pin 64-pin 64-pin 64-pin 64-pin pd78014h m emi-noise reduced version of pd78018f m m pd780058 pd780058y note m m 80-pin serial i/o of the pd78054 was enhanced and emi-noise was reduced. 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. a timer was added to the pd78054 and external interface was enhanced rom-less version of the pd78078 pd78070a pd78070ay m pd78078 pd78078y pd780018 note pd780018y m m m m m m 100-pin serial i/o of the pd78078 was enhanced and the function is limited. m m 100-pin control pd78075b pd78075by m m emi-noise reduced version of pd78078 m inverter control pd780228 100-pin the i/o and fip c/d of the pd78044h were enhanced, display output total: 48 m m m pd780208 100-pin fip tm drive the i/o and fip c/d of the pd78044f were enhanced, display output total: 53 m m pd780208 m pd78098b emi-noise reduced version of the pd78098 m 80-pin m pd780805 100-pin meter control on-chip automobile meter driving controller/driver m pd780973 general purpose version of automobile meter driving controller of the pd780805 m 80-pin m
chapter 1 general 5 the following lists the main functional differences between subseries products. function rom timer 8-bit 10-bit 8-bit serial interface i/o v dd min. external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a value expansion control m pd78075b 32k-40k 4ch 1ch 1ch 1ch 8ch C 2ch 3ch (uart: 1ch) 88 1.8 v m pd78078 48k-60k m pd78070a C 61 2.7 v m pd780018 48k-60k C 2ch (time division 3-wire: 1ch) 88 m pd780058 24k-60k 2ch 2ch 3ch (time division uart: 1ch) 68 1.8 v m pd78058f 48k-60k 3ch (uart: 1ch) 69 2.7 v m pd78054 16k-60k 2.0 v m pd780034 8k-32k C 8ch C 3ch (uart: 1ch, 51 1.8 v m pd780024 8ch C time division 3-wire: 1ch) m pd78014h 2ch 53 1.8 v m pd78018f 8 k-60k m pd78014 8k-32k 2.7 v m pd780001 8k C C 1ch 39 C m pd78002 8k-16k 1ch C 53 m pd78083 C 8ch 1ch (uart: 1ch) 33 1.8 v C inverter m pd780964 8k-32k 3ch note C 1ch C 8ch C 2ch (uart: 2ch) 47 2.7 v control m pd780924 8ch C fip m pd780208 32k-60k 2ch 1ch 1ch 1ch 8ch C C 2ch 74 2.7 v C drive m pd780228 48k-60k 3ch C C 1ch 72 4.5 v m pd78044h 32k-48k 2ch 1ch 1ch 68 2.7 v m pd78044f 16k-40k 2ch lcd m pd780308b 48k-60k 2ch 1ch 1ch 1ch 8ch C C 3ch (time division uart: 1ch) 57 2.0 v C drive m pd78064 32k 2ch (uart: 1ch) m pd78064 16k-32k iebus m pd78098b 40k-60k 2ch 1ch 1ch 1ch 8ch C 2ch 3ch (uart: 1ch) 69 2.7 v supported m pd78098 32k-60k meter m pd780973 24k-32k 3ch 1ch 1ch 1ch 5ch C C 2ch (uart: 1ch) 56 4.5 v C control m pd780805 40k-60k 2ch 8ch 39 2.7 v lv m pd78p0914 32k 6ch C C 1ch 8ch C C 2ch 54 4.5 v note 10-bit timer: 1 channel
chapter 1 general 6 1.6 block diagram 8-bit remote controller timer (tm1) 8-bit pwm timer (tm50) 8-bit pwm timer (tm51) serial interface (sio3) a/d converter (a/d1) interrupt control (int) watchdog timer 78k/0 cpu core ram 1024 bytes rom flash memory port0 port1 port2 port4 port5 port6 port7 port8 port9 port10 p00, p01 p10-p17 p20-p25 p40-p47 p50-p57 p60-p67 p70-p77 p80-p87 p90-p97 p100-p107 fip0-fip47 fip controller/ driver system control ti1/p23 tio50/p24 tio51/p25 sck/p20 so/p21 si/p22 ani0/p10- ani7/p17 av dd av ss intp0/p00 intp1/p01 v load reset x1 x2 v dd0 , v dd1 , v dd2 v ss0 , v ss1 ic (v pp ) remarks 1. the internal rom capacity differs depending on the model. 2. ( ): m PD78F0228
chapter 1 general 7 1.7 functional outline part number m pd780226 m pd780228 m PD78F0228 item internal memory rom mask rom flash memory 48k bytes 60k bytes 60k bytes note high-speed ram 1024 bytes expansion ram 512 bytes fip display ram 96 bytes general-purpose register 8 bits 8 4 banks minimum instruction execution time 0.4/0.8/1.6/3.2/6.4 m s (main system clock: 5.0 mhz) instruction set ? 16-bit operation ? multiplication/division (8 bits 8 bits, 16 bits 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. i/o port ? total : 72 pins (including fip-multiplexed pins) ? cmos input : 8 pin ? cmos i/o : 16 pins ? n-ch open-drain i/o : 16 pins ? p-ch open-drain i/o : 24 pins ? p-ch open-drain output : 8 pins fip controller/driver ? total display output : 48 pins ? display current 10 ma : 16 pins ? display current: 3 ma : 32 pins a/d converter ? 8-bit resolution 8 channels ? supply voltage: av dd = 4.5 to 5.5 v serial interface 3-wire serial i/o mode: 1 channel timer ? 8-bit remote control timer : 1 channel ? 8-bit pwm timer : 2 channels ? watchdog timer : 1 channel timer output 2 pins (8-bit pwm output) vectored maskable internal: 6, external: 4 interrupt source non-maskable internal: 1 software 1 supply voltage v dd = 4.5 to 5.5 v package 100-pin plastic qfp (14 20 mm) note 48k or 60k bytes can be selected by the memory size select register (ims)
chapter 1 general 8 1.8 mask option the mask rom models ( m pd780226 and 780228) have mask options. by specifying the mask options when placing an order for these models, the pull-up and pull-down resistors shown in table 1-1 can be connected. if these mask options are used when pull-up and pull-down resistors are necessary, the number of components can be decreased and the mounting area can be reduced. table 1-1 shows the mask options available for the m pd780228 subseries. table 1-1. mask options of mask rom models pin name mask option p50-p57, p60-p67 pull-up resistors can be connected in 1-bit units. p70/fip16-p77/fip23, pull-down resistors can be connected in 1-bit units. p80/fip24-p87/fip31, p90/fip32-p97/fip39, p100/fip40-p107/fip47
chapter 2 pin functions 9 chapter 2 pin functions 2.1 pin function list (1) port pins (1/2) pin name i/o function at reset shared with: p00 i/o port 0. input intp0 2-bit i/o port. can be set in input or output mode in 1-bit units. p01 internal pull-up resistor can be used via software when this port is intp1 used as input port. p10-p17 input port 1. input ani0-ani7 8-bit input port. p20 i/o port 2. input sck p21 6-bit i/o port. so p22 can be set in input or output mode in 1-bit units. si p23 internal pull-up resistor can be used via software when this port is ti1 p24 used as input port. tio50 p25 tio51 p40-p47 i/o port 4. input 8-bit i/o port. can be set in input or output mode in 1-bit units. can directly drive led. internal pull-up resistor can be used via software when this port is used as input port. p50-p57 i/o port 5. input n-ch open-drain 8-bit medium-voltage i/o port. can be set in input or output mode in 1-bit units. can directly drive led. internal pull-up resistor can be used by mask option in 1-bit units (mask rom models only). m PD78F0228 does not have pull-up resistors, however. p60-p67 i/o port 6. input n-ch open-drain 8-bit medium-voltage i/o port. can be set in input or output mode in 1-bit units. can directly drive led. internal pull-up resistor can be used by mask option in 1-bit units (mask rom models only). m PD78F0228 does not have pull-up resistors, however. p70-p77 i/o port 7. input fip16-fip23 p-ch open-drain 8-bit high-voltage i/o port. can be set in input or output mode in 1-bit units. internal pull-down resistor can be used by mask option in 1-bit units (mask rom models only). m PD78F0228 does not have pull-down resistors, however.
chapter 2 pin functions 10 (1) port pins (2/2) pin name i/o function at reset shared with: p80-p87 i/o port 8. input fip24-fip31 p-ch open-drain 8-bit high-voltage i/o port. can be set in input or output mode in 1-bit units. internal pull-down resistor can be used by mask option in 1-bit units (mask rom models only). m PD78F0228 does not have pull-down resistors, however. p90-p97 i/o port 9. input fip32-fip39 p-ch open-drain 8-bit high-voltage i/o port. can be set in input or output mode in 1-bit units. internal pull-down resistor can be used by mask option in 1-bit units (mask rom models only). m PD78F0228 does not have pull-down resistors, however. p100-p107 output port 10. output fip40-fip47 p-ch open-drain 8-bit high-voltage output port. internal pull-down resistor can be used by mask option in 1-bit units (mask rom models only). m PD78F0228 does not have pull-down resistors, however.
chapter 2 pin functions 11 (2) pins other than port pins pin name i/o function at reset shared with: intp0 input valid edge (rising, falling, or both rising and falling) can be specified. input p00 intp1 external interrupt request input. p01 sck i/o serial clock input/output of serial interface. input p20 so output serial data output of serial interface. input p21 si input serial data input of serial interface. input p22 ti1 input timer input of 8-bit remote control timer (tm1). input p23 tio50 i/o capture trigger input/timer output of 8-bit pwm timer (tm50). input p24 tio51 i/o capture trigger input/timer output of 8-bit pwm timer (tm51). input p25 fip0-fip15 output high-voltage high-current output of fip controller/driver. output fip16-fip23 input p70-p77 fip24-fip31 p80-p87 fip32-fip39 p90-p97 fip40-fip47 p100-p107 v load pull-down resistor connection of fip controller/driver. reset input system reset input. x1 input crystal connection for main system clock oscillation. x2 ani0-ani7 input analog input for a/d converter. input p10-p17 av dd analog power to a/d converter. same potential as v dd1 . av ss ground potential for a/d converter. same potential as v ss1 . v dd0 positive power supply to ports. v dd1 positive power supply (except ports, analog block, and fip controller/driver) v dd2 positive power supply to fip controller/driver. v ss0 ground potential for ports. v ss1 ground potential (except ports and analog block). v pp note high voltage is applied to this pin when program is written/verified. in the normal operation mode, directly connect this pin to v ss1 . ic internally connected. directly connect this pin to v ss1 . note v pp is provided to the m PD78F0228 only.
chapter 2 pin functions 12 2.2 pin functions 2.2.1 p00 and p01 (port 0) p00 and p01 are used as a 2-bit i/o port. these pins also have external interrupt request input functions in addition to the i/o port function. port 0 can be set in the following operation modes in 1-bit units. (1) port mode p00 and p01 function as a 2-bit i/o port in this mode. this 2-bit port can be set in the input or output mode in 1-bit units by the port mode register 0 (pm0). when used as an input port, the internal pull-up resistor can be connected by using the pull-up resistor option register 0 (pu0). (2) control mode p00 and p01 functions as external interrupt request input pins (intp0 and intp1). intp0 and intp1 input external interrupt requests whose valid edge can be specified (to be the rising edge, falling edge, or both the rising and falling edges). 2.2.2 p10 through p17 (port 1) p10 through p17 constitute an 8-bit input port, port 1. this port is also used to input analog signals to the internal a/d converter. the following operation modes can be specified in 1-bit units. (1) port mode port 1 functions as an 8-bit input port in this mode. (2) control mode p10 through p17 function as analog input pins (ani0 through ani7) of the a/d converter. 2.2.3 p20 through p25 (port 2) p20 through p25 constitute a 6-bit i/o port, port 2. these pins also have functions to input/output data of the serial interface, clock, and timer signals. the following operation modes can be specified in 1-bit units. (1) port mode in this mode, p20 through p25 function as a 6-bit i/o port. this port can be set in the input or output mode in 1-bit units by using the port mode register 2 (pm2). when the port is used as an input port, the internal pull- up resistor can be used if so specified by the pull-up resistor option register 2 (pu2). (2) control mode in this mode, p20 through p25 are used to input/output serial interface data, clock, and timer signal, and input timers capture trigger signals. (a) si, so these are i/o pins of the serial data of the serial interface. (b) sck this is an i/o pin of the serial clock of the serial interface.
chapter 2 pin functions 13 (c) ti1 timer input pin of the 8-bit remote control timer. (d) tio50 and tio51 capture trigger input pin of the 8-bit pwm timers and timer output pin. 2.2.4 p40 through p47 (port 4) p40 through 47 constitute an 8-bit i/o port. this port can be set in the input or output mode in 1-bit units by using the port mode register 4 (pm4). when it is used as an input port, the internal pull-up resistor can be connected by using the pull-up resistor option register 4 (pu4). this port can directly drive an led. 2.2.5 p50 through p57 (port 5) p50 through 57 constitute an 8-bit i/o port. this port can be set in the input or output mode in 1-bit units by using the port mode register 5 (pm5). p50 through p57 are n-ch open-drain pins. pull-up resistors can be connected to these pins of the mask rom models by mask option. the m PD78F0228 does not have pull-up resistors. this port can directly drive an led. 2.2.6 p60 through p67 (port 6) p60 through 67 constitute an 8-bit i/o port. this port can be set in the input or output mode in 1-bit units by using the port mode register 6 (pm6). p60 through p67 are n-ch open-drain pins. pull-up resistors can be connected to these pins of the mask rom models by mask option. the m PD78F0228 does not have pull-up resistors. this port can directly drive an led. 2.2.7 p70 through p77 (port 7) p70 through p77 constitute an 8-bit i/o port. these pins are also used as fip controller/driver output pins. the following operation modes can be specified in 1-bit units. (1) port mode p70 through p77 function as an 8-bit i/o port in this mode. these pins are p-ch open-drain pins. pull-down resistors can be connected to these pins of the mask rom models by mask option. the m PD78F0228 does not have pull-down resistors. (2) control mode in this mode, p70 through p77 function as the output pins of the fip controller/driver (fip16 through fip23). 2.2.8 p80 through p87 (port 8) p80 through p87 constitute an 8-bit i/o port. these pins are also used as fip controller/driver output pins. the following operation modes can be specified in 1-bit units. (1) port mode p80 through p87 function as an 8-bit i/o port in this mode. these pins are p-ch open-drain pins. pull-down resistors can be connected to these pins of the mask rom models by mask option. the m PD78F0228 does not have pull-down resistors. (2) control mode in this mode, p80 through p87 function as the output pins of the fip controller/driver (fip24 through fip31).
chapter 2 pin functions 14 2.2.9 p90 through p97 (port 9) p90 through p97 constitute an 8-bit i/o port. these pins are also used as fip controller/driver output pins. the following operation modes can be specified in 1-bit units. (1) port mode p90 through p97 function as an 8-bit i/o port in this mode. these pins are p-ch open-drain pins. pull-down resistors can be connected to these pins of the mask rom models by mask option. the m PD78F0228 does not have pull-down resistors. (2) control mode in this mode, p90 through p97 function as the output pins of the fip controller/driver (fip32 through fip39). 2.2.10 p100 through p107 (port 10) p100 through p107 constitute an 8-bit output port. these pins are also used as fip controller/driver output pins. the following operation modes can be specified in 1-bit units. (1) port mode p100 through p107 function as an 8-bit output port in this mode. these pins are p-ch open-drain pins. pull-down resistors can be connected to these pins of the mask rom models by mask option. the m PD78F0228 does not have pull-down resistors. (2) control mode in this mode, p100 through p107 function as the output pins of the fip controller/driver (fip40 through fip47). 2.2.11 fip0 through fip15 these are the output pins of the fip controller/driver. 2.2.12 v load this pin connects a pull-down resistor to the fip controller/driver. 2.2.13 av dd this pin supply an analog voltage to the a/d converter. always keep this pin at the same potential as the v dd1 pin even when the a/d converter is not used. 2.2.14 av ss this is the ground pin of the a/d converter. always keep this pin at the same potential as the v ss1 pin even when the a/d converter is not used. 2.2.15 reset this pin inputs an active-low system reset signal. 2.2.16 x1 and x2 these pins connect a crystal resonator for main system clock oscillation. to supply an external clock, input it to x1, and input a signal reverse to that input to x1, to x2.
chapter 2 pin functions 15 2.2.17 v dd0 through v dd2 v dd0 supplies a positive voltage to the ports. v dd1 supplies a positive voltage to the internal function blocks other than the ports, analog block, and fip controller/ driver. v dd2 supplies a positive voltage to the fip controller/driver. 2.2.18 v ss0 and v ss1 v ss0 is the ground pin for the ports. v ss1 is the ground pin for the internal function blocks other than the ports and analog block. 2.2.19 v pp ( m m m m m PD78F0228 only) a high voltage is applied to this pin when the flash memory programming mode is used and when a program is written or verified. directly connect this pin to v ss1 in the normal operation mode. 2.2.20 ic (mask rom product only) the ic (internally connected) pin sets a test mode in which the m pd780226 and 780228 are tested before shipment. usually, connect the ic pin directly to v ss1 with as short a wiring length as possible. if there is a potential difference between the ic and v ss1 pins because the wiring length between the ic and v ss1 pin is too long, or external noise is superimposed on the ic pin, your program may not run correctly. directly connect the ic pin to the v ss1 . v ss1 ic keep the wiring length as short as possible.
chapter 2 pin functions 16 2.3 i/o circuits of pins and connections of unused pins table 2-1 shows the i/o circuit types of the respective pins, and the recommended connections of each pin when it is not used. for the configuration of each type of the i/o circuit, refer to figure 2-1. table 2-1. i/o circuit type of each pin pin name i/o circuit type i/o recommended connections of unused pin p00/intp0 8-c i/o individually connect to v ss0 via resistor. p01/intp1 p10/ani0-p17/ani7 9 input p20/sck 8-c i/o individually connect to v dd0 or v ss0 via resistor. p21/so 5-h p22/si 8-c p23/ti1 p24/tio50 p25/tio51 p40-p47 mask rom model p50-p57 13-j i/o individually connect to v dd0 via resistor. p60-p67 p70/fip16-p77/fip23 15-f i/o individually connect to v dd0 or v ss0 via resistor. p80/fip24-p87/fip31 p90/fip32-p97/fip39 p100/fip40-p107/fip47 14-f output ic directly connect to v ss1 . m PD78F0228 p50-p57 13-k i/o individually connect to v dd0 via resistor. p60-p67 p70/fip16-p77/fip23 15-e i/o individually connect to v dd0 or v ss0 via resistor. p80/fip24-p87/fip31 p90/fip32-p97/fip39 p100/fip40-p107/fip47 14-e output v pp directly connect to v ss1 . fip0-fip15 14-c output individually connect to v dd0 or v ss0 via resistor. reset 2 input av dd connect to v dd1 . av ss connect to v ss1 . v load
chapter 2 pin functions 17 figure 2-1. pin input/output circuit list (1/2) in pull-up enable v dd0 p-ch in/out input enable output disable data v dd0 p-ch n-ch type 2 type 5-h schmitt-triggered input with hysteresis characteristics type 8-c pull-up enable v dd0 p-ch in/out output disable data v dd0 p-ch n-ch type 9 type 13-j type 13-k data v dd0 n-ch p-ch in/out v dd0 output disable rd medium-voltage input buffer mask option v ss0 v ss0 v ss0 p-ch n-ch in input enable v ref comparator (threshold voltage) + data n-ch p-ch in/out v dd0 output disable rd medium-voltage input buffer v ss0
chapter 2 pin functions 18 figure 2-1. pin input/output circuit list (2/2) type 14-c v dd0 p-ch n-ch v dd0 p-ch data out v load mask option type 14-f v dd0 v dd0 p-ch p-ch n-ch in/out data mask option v load rd n-ch type 15-f type 15-e type 14-e v dd0 v dd0 p-ch p-ch n-ch out data v load v ss0 v dd0 v dd0 p-ch p-ch n-ch in/out data rd n-ch v ss0 v ss0 v dd0 v dd0 p-ch p-ch n-ch out data v ss0 v ss0 v ss0 v ss0
chapter 3 cpu architecture 19 chapter 3 cpu architecture 3.1 memory space each model in the m pd780228 subseries can access a memory space of 64k bytes. figures 3-1 through 3-3 show the memory map. figure 3-1. memory map ( m m m m m pd780226) special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits fip display ram 96 8 bits cannot be used cannot be used internal rom 49152 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area internal expansion ram 512 8 bits cannot be used ffffh ff00h feffh fee0h fedfh fb00h faffh fa60h fa5fh fa00h f9ffh f800h f7ffh f600h f5ffh c000h bfffh 0000h bfffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h
chapter 3 cpu architecture 20 figure 3-2. memory map ( m m m m m pd780228) special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits fip display ram 96 8 bits cannot be used internal rom 61440 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area internal expansion ram 512 8 bits cannot be used ffffh ff00h feffh fee0h fedfh fb00h faffh fa60h fa5fh fa00h f9ffh f800h f7ffh f600h f5ffh f000h efffh 0000h efffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h cannot be used
chapter 3 cpu architecture 21 figure 3-3. memory map ( m m m m m PD78F0228) special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits fip display ram 96 8 bits cannot be used flash memory 61440 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area internal expansion ram 512 8 bits cannot be used ffffh ff00h feffh fee0h fedfh fb00h faffh fa60h fa5fh fa00h f9ffh f800h f7ffh f600h f5ffh f000h efffh 0000h efffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h cannot be used
chapter 3 cpu architecture 22 3.1.1 internal program memory space the internal program memory space stores programs and table data. usually, this space is accessed by program counter (pc). each model in the m pd780228 subseries has an internal rom (or flash memory) of the following capacity. table 3-1. internal rom capacity part number internal rom structure capacity m pd780226 mask rom 49152 8 bits m pd780228 61440 8 bits m PD78F0228 flash memory the following areas are allocated to the internal program memory space. (1) vector table area a 64-byte area of addresses 0000h through 003fh is reserved as a vector table area. program start addresses to which execution is to branch when the reset signal is input or when an interrupt request is generated are stored in this area. of a 16-bit address, the low-order 8 bits are stored to an even address, and the high-order 8 bits are stored to an odd address. table 3-2. vector table vector table address interrupt request vector table address interrupt request 0000h reset input 000eh intks 0004h intwdt 0010h intcsi3 0006h intp0 0012h inttm50 0008h intp1 0014h inttm51 000ah inttm10 0016h intad 000ch inttm11 003eh brk (2) callt instruction table area the 64-byte area 0040h through 007fh can be used to store the subroutine entry addresses of the 1-byte call instruction (callt). (3) callf instruction entry area from an area of 0800h through 0fffh, a subroutine can be directly called by using the 2-byte call instruction (callf).
chapter 3 cpu architecture 23 3.1.2 internal data memory space the m pd780228 subseries has the following ram. (1) internal high-speed ram this ram consists of addresses fb00h through feffh, or 1024 8 bits. of these addresses, fee0h through feffh constitute a 32-byte area to which four banks of general-purpose registers, with each bank consisting of eight 8-bit registers, are allocated. the internal high-speed ram can be also used as a stack memory. (2) internal expansion ram an internal expansion ram is allocated to a 512-byte area of f600h through f7ffh. (3) fip display ram an fip display ram is allocated to a 96-byte area of fa00h through f5fh. this ram can be also used as a normal ram. 3.1.3 special function register (sfr) area special function registers (sfr) are allocated to the area ff00h through ffffh as on-chip peripheral hardware (refer to table 3-3 special function registers in 3.2.3 special function register (sfr)) . caution do not access an address to which no sfr is allocated.
chapter 3 cpu architecture 24 3.1.4 data memory addressing specifying the address of the instruction to be executed next, or specifying an address of the register or memory to be manipulated when an instruction is executed is called addressing. the address of the instruction to be executed next is addressed by the program counter (pc) (for details, refer to 3.3 addressing of instruction address ). the m pd780288 subseries has many addressing modes to improve the operability when a memory area to be manipulated during instruction execution is addressed. the special function registers (sfr) and general-purpose registers can be addressed in accordance with their functions. all the 64k bytes of the data memory, 0000h through ffffh, can be also addressed. figures 3-4 through 3-6 illustrates how the data memory is addressed. for details on each addressing mode, refer to 3.4 addressing of operand address .
chapter 3 cpu architecture 25 figure 3-4. addressing of data memory ( m m m m m pd780226) short direct addressing sfr addressing register addressing direct addressing register indirect addressing based addressing based indexed addressing ffffh ff20h ff1fh ff00h feffh fee0h fedfh fe20h fe1fh fb00h faffh fa60h fa5fh fa00h f9ffh f800h f7ffh f600h f5ffh c000h bfffh 0000h special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits fip display ram 96 8 bits cannot be used internal rom 49152 8 bits internal expansion ram 512 8 bits cannot be used cannot be used
chapter 3 cpu architecture 26 figure 3-5. addressing of data memory ( m m m m m pd780228) short direct addressing sfr addressing register addressing direct addressing register indirect addressing based addressing based indexed addressing ffffh ff20h ff1fh ff00h feffh fee0h fedfh ff20h fe1fh fb00h faffh fa60h fa5fh fa00h f9ffh f800h f7ffh f600h f5ffh f000h efffh 0000h special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits fip display ram 96 8 bits cannot be used internal rom 61440 8 bits internal expansion ram 512 8 bits cannot be used cannot be used
chapter 3 cpu architecture 27 figure 3-6. addressing of data memory ( m m m m m PD78F0228) short direct addressing sfr addressing register addressing direct addressing register indirect addressing based addressing based indexed addressing ffffh ff20h ff1fh ff00h feffh fee0h fedfh fe20h fe1fh fb00h faffh fa60h fa5fh fa00h f9ffh f800h f7ffh f600h f5ffh f000h efffh 0000h special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits fip display ram 96 8 bits cannot be used flash memory 61440 8 bits internal expansion ram 512 8 bits cannot be used cannot be used
chapter 3 cpu architecture 28 3.2 processor registers the m pd780228 subseries units incorporate the following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses and stack memory. a program counter (pc), a program status word (psw) and a stack pointer (sp) are control registers. (1) program counter (pc) the program counter is a 16-bit register which holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data and register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-7. program counter configuration (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically reset upon execution of the retb, reti and pop psw instructions. reset input sets the psw to 02h. figure 3-8. program status word configuration (a) interrupt enable flag (ie) this flag controls interrupt request acknowledge operations of cpu. when ie = 0, all interrupts, except the non-maskable interrupt, are disabled (di status). when ie = 1, the interrupts are enabled (ei status). at this time, acknowledging interrupts is controlled with an inservice priority flag (isp) and an interrupt mask flag for various interrupt sources and a priority specify flag. the interrupt enable flag is also reset to 0 when the di instruction or an interrupt request has been acknowledged and is set to 1 when the ei instruction has been executed. (b) zero flag (z) when the operation result is zero, this flag is set (1). it is reset (0) in all other cases. 70 ie z rbs1 ac rbs0 0 isp cy psw pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 15 0 pc
chapter 3 cpu architecture 29 (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information which indicates the register bank selected by sel rbn instruction execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable maskable vectored interrupts. when isp = 0, the vectored interrupt request specified by the priority specify flag registers (pr0l and pr0h) (refer to 12.3 (3) priority specify flag registers (pr0l and pr0h) ) to have a low priority is disabled. whether an interrupt request is actually acknowledged is controlled by the status of the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high-speed ram area (fb00h to feffh) can be set as the stack area. figure 3-9. stack pointer configuration the sp is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory. each stack operation saves/restores data as shown in figures 3-10 and 3-11. caution since reset input makes sp contents indeterminate, be sure to initialize the sp before instruction execution. sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 15 0 sp
chapter 3 cpu architecture 30 figure 3-10. data to be saved to stack memory figure 3-11. data to be restored from stack memory interrupt and brk instruction call, callf, and callt instruction push rp instruction register pair lower register pair upper sp sp ?2 sp ?2 sp ?1 sp sp sp ?2 sp ?2 sp ?1 sp pc7 to pc0 pc15 to pc8 sp sp ?3 sp ?3 sp ?2 sp ?1 pc15 to pc8 psw sp pc7 to pc0 reti and retb instruction pc15 to pc8 psw pc7 to pc0 sp sp + 3 sp sp + 1 sp + 2 pc15 to pc8 pc7 to pc0 sp sp + 2 sp sp + 1 register pair lower sp sp + 2 sp sp + 1 register pair upper ret instruction pop rp instruction
chapter 3 cpu architecture 31 3.2.2 general registers a general register is mapped at particular addresses (fee0h to feffh) of the data memory. it consists of 4 banks, each bank consisting of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can also be used as an 8-bit register. two 8-bit registers can be used in pairs as a 16-bit register (ax, bc, de, and hl). they can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set with the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interruption for each bank. figure 3-12. general register configuration (a) absolute name (b) function name bank0 bank1 bank2 bank3 feffh fef8h fef0h fee8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing bank0 bank1 bank2 bank3 feffh fef8h fef0h fee8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing
chapter 3 cpu architecture 32 3.2.3 special function registers (sfr: special function register) unlike a general register, each special function register has special functions. it is allocated in the ff00h to ffffh area. the special function register can be manipulated, like the general register, with the operation, transfer and bit manipulation instructions. manipulatable bit units, 1, 8, and 16, depend on the special function register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp). when addressing an address, describe an even address. table 3-3 gives a list of special function registers. the meaning of items in the table is as follows. ? symbol this is a symbol to indicate an address of the special function register. the symbols shown in this column are reserved words of the ra78k/0, and have already been defined in the header file called sfrbit.h of the cc78k/0. these are describable as instruction operands if the ra78k/0, id78k0, or sd78k/0 is used. ? r/w indicates whether the corresponding special function register can be read or written. r/w : read/write enable r : read only w : write only ? manipulatable bit units indicates the bit unit (1, 8, or 16 bits) in which the register can be manipulated. C indicates that the register cannot be manipulated in the indicated bit unit. ? at reset indicates each register status upon reset input.
chapter 3 cpu architecture 33 table 3-3. special function registers (1/2) address special function register (sfr) name symbol r/w manipulatable bit units at reset 1 bit 8 bits 16 bits ff00h port 0 p0 r/w 00h ff01h port 1 p1 r ff02h port 2 p2 r/w ff04h port 4 p4 ff05h port 5 p5 ff06h port 6 p6 ff07h port 7 p7 ff08h port 8 p8 ff09h port 9 p9 ff0ah port 10 p10 ff0bh port read 7 plr7 r undefined ff0ch port read 8 plr8 ff0dh port read 9 plr9 ff0eh 8-bit capture register 10 cp10 00h ff0fh 8-bit capture register 11 cp11 ff10h 8-bit compare register 50 cr50 r/w undefined ff11h 8-bit compare register 51 cr51 ff12h 8-bit counter 50 tm5 tm50 r 00h ff13h 8-bit counter 51 tm51 ff14h a/d conversion result register adcrh0 undefined ff18h serial i/o shift register 3 sio3 r/w ff20h port mode register 0 pm0 ffh ff22h port mode register 2 pm2 ff24h port mode register 4 pm4 ff25h port mode register 5 pm5 ff26h port mode register 6 pm6 ff30h pull-up resistor option register 0 pu0 00h ff32h pull-up resistor option register 2 pu2 ff34h pull-up resistor option register 4 pu4 ff42h watchdog timer clock select register wdcs ff48h external interrupt rising edge enable register egp ff49h external interrupt falling edge enable register egn ff60h timer mode control register 1 tmc1 ff70h 8-bit timer mode control register 50 tmc50 04h ff71h timer clock select register 50 tcl50 00h ff78h 8-bit timer mode control register 51 tmc51 04h ff79h timer clock select register 51 tcl51 00h ff80h a/d converter mode register adm0 ff81h analog input channel specification register ads0 ff86h serial operation mode register 3 csim3
chapter 3 cpu architecture 34 table 3-3. special function registers (2/2) address special function register (sfr) name symbol r/w manipulatable bit units at reset 1 bit 8 bits 16 bits ff90h display mode register 0 dspm0 r/w 10h ff91h display mode register 1 dspm1 01h ff92h display mode register 2 dspm2 00h ffe0h interrupt request flag register 0l if0 if0l 00h ffe1h interrupt request flag register 0h if0h ffe4h interrupt mask flag register 0l mk0 mk0l ffh ffe5h interrupt mask flag register 0h mk0h ffe8h priority specification flag register 0l pr0 pr0l ffe9h priority specification flag register 0h pr0h fff0h memory size select register ims cch note 1 fff4h internal expansion ram size select register ixs 0ch note 2 fff9h watchdog timer mode register wdtm 00h fffah oscillation stabilization time select register osts 04h fffbh processor clock control register pcc notes 1. be sure to set the value of this register to cfh when the m pd780228 is used. 2. after reset, be sure to set this bit to 0bh.
chapter 3 cpu architecture 35 3.3 addressing of instruction address an instruction address is determined by program counter (pc) contents. program counter (pc) contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing (for details of instructions, refer to 78k/0 series users manual: instructions (u12326e) . 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed twos complement data (C128 to +127) and bit 7 becomes a sign bit. in the relative addressing modes, execution branches in a relative range of C128 to +127 from the first address of the next instruction. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. [illustration] 15 0 pc + 15 0 876 s 15 0 pc a jdisp8 when s = 0, all bits of a are 0. when s = 1, all bits of a are 1. pc indicates the start address of the instruction after the br instruction. ...
chapter 3 cpu architecture 36 3.3.2 immediate addressing [function] immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. the call !addr16 and br !addr16 instruction can branch in the entire memory space. the callf !addr11 instruction branches to an area of addresses 0800h to 0fffh. [illustration] in the case of call !addr16 and br !addr16 instructions in the case of callf !addr11 instruction 15 0 pc 87 70 call or br low addr. high addr. 15 0 pc 87 70 fa 10 to 8 11 10 00001 643 callf fa 7 to 0
chapter 3 cpu architecture 37 3.3.3 table indirect addressing [function] table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (pc) and branched. before the callt [addr5] instruction is executed, table indirect addressing is performed. this instruction references an address stored in the memory table at addresses 40h to 7fh, and can branch in the entire memory space. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address + 1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4 to 0 operation code
chapter 3 cpu architecture 38 3.3.4 register addressing [function] register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) and branched. this function is carried out when the br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
chapter 3 cpu architecture 39 3.4 addressing of operand address the following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 implied addressing [function] the register which functions as an accumulator (a and ax) in the general register is automatically (tacitly) addressed. of the pd780228 subseries instruction words, the following instructions employs implied addressing. instruction register to be specified by implied addressing mulu a register for multiplicand and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric values subject to decimal adjustment ror4/rol4 a register for storage of digit data which undergoes digit rotation [operand format] because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit x 8-bit multiply instruction, the product of a register and x register is stored in ax. in this example, the a and ax registers are specified by implied addressing.
chapter 3 cpu architecture 40 3.4.2 register addressing [function] this addressing accesses a general register as an operand. the general register accessed is specified by the register bank select flags (rbs0 and rbs1) and register specify code (rn or rpn) in an instruction code. register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl r and rp can be described with function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) as well as absolute names (r0 to r7 and rp0 to rp3). [description example] mov a, c; when selecting c register as r incw de; when selecting de register pair as rp operation code 01100010 operation code 10000100 register specify code register specify code
chapter 3 cpu architecture 41 3.4.3 direct addressing [function] this addressing directly addresses the memory indicated by the immediate data in an instruction word. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe00h; when setting !addr16 to fe00h [illustration] operation code 10001110 00000000 11111110 op code 00h ffh 70 op code addr16 (lower) memory addr16 (higher)
chapter 3 cpu architecture 42 3.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. the fixed space to which this addressing is applied is the 256-byte space of addresses fe20h to ff1fh. addresses fe20h to feffh constitute a part of the sfr area, and the internal high-speed ram is mapped to this area. the special function registers (sfrs) are mapped to the area from addresses ff00h to ff1fh. if the sfr area (ff00h to ff1fh) where short direct addressing is applied, ports which are frequently accessed in a program and a compare register of the timer/event counter and a capture register of the timer/event counter are mapped and these sfrs can be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. refer to [illustration] on the next page. [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label of fe20h to ff1fh immediate data (even address only)
chapter 3 cpu architecture 43 [description example] mov 0fe30h, #50h; when setting saddr to fe30h and immediate data to 50h [illustration] operation code 00010001 00110000 01010000 15 0 70 op code saddr-offset effective address 8 when 8-bit immediate data is 20h to ffh, a = 0 a 1111111 short direct memory when 8-bit immediate data is 00h to 1fh, a = 1 op code 30h (saddr to offset) 50h (immediate data)
chapter 3 cpu architecture 44 3.4.5 special function register (sfr) addressing [function] the memory-mapped special function register (sfr) is addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfr mapped at ff00h to ff1fh can be accessed with short direct addressing. [operand format] identifier description sfr special function register name sfrp 16-bit manipulatable special function register name (even address only) [description example] mov pm0, a; when selecting pm0 (ff20h) as sfr [illustration] operation code 11110110 00100000 15 0 70 op code sfr-offset effective address 8 1111111 7 1 sfr op code 20h (sfr to offset)
chapter 3 cpu architecture 45 3.4.6 register indirect addressing [function] the addressing addresses the memory with the contents of a register pair specified as an operand. the register pair to be accessed is specified by the register bank select flags (rbs0 and rbs1) and register pair specify code in an instruction code. this addressing can be carried out for all the memory spaces. [operand format] identifier description [de], [hl] [description example] mov a, [de]; when selecting [de] as register pair [illustration] operation code 10000101 15 0 7 8 de 70 a 0 7 de memory address specified by register pair de. contents of addressed memory are transferred. memory
chapter 3 cpu architecture 46 3.4.7 based addressing [function] this addressing addresses the memory by adding 8-bit immediate data to the contents of the hl register pair which is used as a base register and by using the result of the addition. the hl register pair to be accessed is in the register bank specified by the register bank select flags (rbs0 and rbs1). addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description [hl+byte] [description example] mov a, [hl+10h]; when setting byte to 10h operation code 10101110 00010000
chapter 3 cpu architecture 47 3.4.8 based indexed addressing [function] this addressing addresses the memory by adding the contents of the hl register pair, which is used as a base register, to the contents of the b or c register specified in the instruction word, and by using the result of the addition. the hl, b, and c registers to be accessed are registers in the register bank specified by the register bank select flags (rbs0 and rbs1). the addition is performed by extending the contents of the b or c register to 16 bits as a positive number. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description [hl+b], [hl+c] [description example] in the case of mov a, [hl+b] 3.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. stack addressing enables to address the internal high-speed ram area only. [description example] in the case of push de operation code 10101011 operation code 10110101
chapter 3 cpu architecture 48 [memo]
chapter 4 port functions 49 chapter 4 port functions 4.1 port functions the m pd780228 subseries incorporates eight input ports, eight output ports and 56 input/output ports. figure 4- 1 shows the port configuration. every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. besides port functions, the ports can also serve as built-in hardware input/output pins. figure 4-1. port types port 7 p70 p77 p80 p90 p97 p100 p107 p10 p17 p20 p25 p40 p47 p50 p57 p00 p60 p67 port 6 port 8 port 9 port 10 port 1 port 0 port 2 port 4 port 5 p87 p01
chapter 4 port functions 50 table 4-1. port function pin name function shared with: p00 port 0. intp0 2-bit i/o port. p01 can be set in input or output mode in 1-bit units. intp1 internal pull-up resistor can be used via software when this port is used as input port. p10-p17 port 1. ani0-ani7 8-bit input port. p20 port 2. sck p21 6-bit i/o port. so p22 can be set in input or output mode in 1-bit units. si p23 internal pull-up resistor can be used via software when this port is used as input port. ti1 p24 tio50 p25 tio51 p40-p47 port 4. 8-bit i/o port. can be set in input or output mode in 1-bit units. can directly drive led. internal pull-up resistor can be used via software when this port is used as input port. p50-p57 port 5. n-ch open-drain 8-bit medium-voltage i/o port. can be set in input or output mode in 1-bit units. can directly drive led. internal pull-up resistor can be used by mask option in 1-bit units (mask rom models only). m PD78F0228 does not have pull-up resistors, however. p60-p67 port 6. n-ch open-drain 8-bit medium-voltage i/o port. can be set in input or output mode in 1-bit units. can directly drive led. internal pull-up resistor can be used by mask option in 1-bit units (mask rom models only). m PD78F0228 does not have pull-up resistors, however. p70-p77 port 7. fip16-fip23 p-ch open-drain 8-bit high-voltage i/o port. can be set in input or output mode in 1-bit units. internal pull-down resistor can be used by mask option in 1-bit units (mask rom models only). m PD78F0228 does not have pull-down resistors, however. p80-p87 port 8. fip24-fip31 p-ch open-drain 8-bit high-voltage i/o port. can be set in input or output mode in 1-bit units. internal pull-down resistor can be used by mask option in 1-bit units (mask rom models only). m PD78F0228 does not have pull-down resistors, however. p90-p97 port 9. fip32-fip39 p-ch open-drain 8-bit high-voltage i/o port. can be set in input or output mode in 1-bit units. internal pull-down resistor can be used by mask option in 1-bit units (mask rom models only). m PD78F0228 does not have pull-down resistors, however. p100-p107 port 10. fip40-fip47 p-ch open-drain 8-bit high-voltage output port. internal pull-down resistor can be used by mask option in 1-bit units (mask rom models only). m PD78F0228 does not have pull-down resistors, however.
chapter 4 port functions 51 4.2 port configuration a port consists of the following hardware. table 4-2. port configuration item configuration control register port mode register (pmm: m = 0, 2, 4-6) pull-up resistor option register (pun: n = 0, 2, 4) port total: 72 (8 inputs, 8 outputs, 56 inputs/outputs) pull-up resistor ? mask rom model total: 32 (software control: 16, mask option control: 16) ? m PD78F0228 total: 16 pull-down resistor ? mask rom product total: 32 (mask option control: 32) ? m PD78F0228 none 4.2.1 port 0 port 0 is a 2-bit input/output port with output latch. p00 and p01 pins can specify the input mode/output mode in 1-bit units with the port mode register 0 (pm0). when p00 and p01 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up resistor option register 0 (pu0). alternate functions include external interrupt request input. reset input sets port 0 to input mode. figure 4-2 shows a block diagram of port 0. caution because port 0 also serves for external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. thus, when the output mode is used, set the interrupt mask flag to 1.
chapter 4 port functions 52 figure 4-2. p00 and p01 block diagram pu : pull-up resistor option register pm : port mode register rd : port 0 read signal wr : port 0 write signal p-ch wr pm wr port rd wr pu v dd0 p00/intp0, p01/intp1 selector pu00, pu01 output latch (p00 and p01) pm00 and pm01 internal bus
chapter 4 port functions 53 4.2.2 port 1 port 1 is an 8-bit input only port. a/d converter analog input is provided as an alternate function. figure 4-3 shows a block diagram of port 1. figure 4-3. p10 to p17 block diagram rd : port 1 read signal rd p10/ani0 to p17/ani7 internal bus
chapter 4 port functions 54 4.2.3 port 2 port 2 is a 6-bit input/output port with output latch. p20 to p25 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (pm2). when p20 to p25 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up resistor option register 2 (pu2). alternate functions include serial interface data input/output, clock input/output, and timer input/output. reset input sets port 2 to input mode. figures 4-4 and 4-5 show block diagrams of port 2. figure 4-4. p20 block diagram pu : pull-up resistor option register pm : port mode register rd : port 2 read signal wr : port 2 write signal p-ch wr pm wr port rd wr pu v dd0 p20/sck selector pu20 output latch (p20) pm20 alternate function internal bus
chapter 4 port functions 55 figure 4-5. p21 to p25 block diagram pu : pull-up resistor option register pm : port mode register rd : port 2 read signal wr : port 2 write signal p-ch wr pm wr port rd wr pu v dd0 p21/so, p22/si, p23/ti1, p24/tio50, p25/tio51 selector pu21-pu25 output latch (p21-p25) pm21-pm25 alternate function internal bus
chapter 4 port functions 56 4.2.4 port 4 port 4 is an 8-bit input/output port with output latch. p40 to p47 pins can specify the input mode/output mode in 1-bit units with the port mode register 4 (pm4). when p40 to p47 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up resistor option register 4 (pu4). port 4 can drive leds directly. reset input sets port 4 to input mode. figure 4-6 shows a block diagram of port 4. figure 4-6. p40 to p47 block diagram pu : pull-up resistor option register pm : port mode register rd : port 4 read signal wr : port 4 write signal wr pm wr port rd p40-p47 selector output latch (p40-p47) pm40-pm47 internal bus p-ch wr pu v dd0 pu40-pu47
chapter 4 port functions 57 4.2.5 port 5 port 5 is an 8-bit input/output port with output latch. pins from 50 to 57 can specify i/o mode in 1-bit units with the port mode register 5 (pm5). on-chip pull-up resistors can be connected in 1-bit units with the mask option in case of mask rom model. the m PD78F0228 has no pull-up resistor. port 5 can drive leds directly. reset input sets port 5 to input mode. figure 4-7 shows a block diagram of port 5. caution low-level input leak current in p50 to p57 pins differs depending on the following conditions: [mask rom model] when pull-up resistors are contained : always C3 m m m m m a (max.) when pull-up resistors are not contained : ? 1 clock interval when read instruction is executed to port 5 (p5) and port mode register 5 (pm5) : C200 m m m m m a (max.) ? other than above : C3 m m m m m a (max.) [flash memory model] ? 1 clock interval when read instruction is executed to port 5 (p5) and port mode register 5 (pm5) : C200 m m m m m a (max.) ? other than above : C3 m m m m m a (max.) figure 4-7. p50 to p57 block diagram pm : port mode register rd : port 5 read signal wr : port 5 write signal internal bus output latch (p50-p57) wr port pm50 to pm57 wr pm selector rd v dd0 mask option mask rom model only. PD78F0228 has no pull-up resistor. p50-p57 m
chapter 4 port functions 58 4.2.6 port 6 port 6 is an 8-bit input/output port with output latch. pins from 60 to 67 can specify i/o mode in 1-bit units with the port mode register 6 (pm6). on-chip pull-up resistors can be connected in 1-bit units with the mask option in case of mask rom model. the m PD78F0228 has no pull-up resistor. port 6 can drive leds directly. reset input sets port 6 to input mode. figure 4-8 shows a block diagram of port 6. caution low-level input leak current in p60 to p67 pins differs depending on the following conditions: [mask rom model] when pull-up resistors are contained : always C3 m m m m m a (max.) when pull-up resistors are not contained : ? 1 clock interval when read instruction is executed to port 6 (p6) and port mode register 6 (pm6) : C200 m m m m m a (max.) ? other than above : C3 m m m m m a (max.) [flash memory model] ? 1 clock interval when read instruction is executed to port 6 (p6) and port mode register 6 (pm6) : C200 m m m m m a (max.) ? other than above : C3 m m m m m a (max.) figure 4-8. p60 to p67 block diagram pm : port mode register rd : port 6 read signal wr : port 6 write signal internal bus output latch (p60-p67) wr port pm60 to pm67 wr pm selector rd v dd0 mask option mask rom model only. PD78F0228 has no pull-up resistor. p60-p67 m
chapter 4 port functions 59 4.2.7 port 7 port 7 is an 8-bit input/output port with output latch. when using this port as an output port, the value assigned to the output latch (p70 through p77) is output. when it is used as an input port, set the output latch (p70 through p77) to 0, and read the port read (plr70 through plr77). on-chip pull-down resistors can be connected in 1-bit units with the mask option. the m PD78F0228 has no pull-down resistor. in addition, fip controller/driver output is provided as an alternate function. reset input sets port 7 to input mode. figure 4-9 shows a block diagram of port 7. figure 4-9. p70 to p77 block diagram rd : port 7 read signal wr : port 7 write signal internal bus output latch (p70-p77) wr port port read (plr70-plr77) rd mask option p70/fip16- p77/fip23 alternate function v load mask rom model only. PD78F0228 has no pull-down resistor. m
chapter 4 port functions 60 4.2.8 port 8 port 8 is an 8-bit input/output port with output latch. when using this port as an output port, the value assigned to the output latch (p80 through p87) is output. when it is used as an input port, set the output latch (p80 through p87) to 0, and read the port read (plr80 through plr87). on-chip pull-down resistors can be connected in 1-bit units with the mask option. the m PD78F0228 has no pull-down resistor. in addition, fip controller/driver output is provided as an alternate function. reset input sets port 8 to input mode. figure 4-10 shows a block diagram of port 8. figure 4-10. p80 to p87 block diagram rd : port 8 read signal wr : port 8 write signal internal bus output latch (p80-p87) wr port port read (plr80-plr87) rd mask option p80/fip24- p87/fip31 alternate function mask rom model only. PD78F0228 has no pull-down resistor. m v load
chapter 4 port functions 61 4.2.9 port 9 port 9 is an 8-bit input/output port with output latch. when using this port as an output port, the value assigned to the output latch (p90 through p97) is output. when it is used as an input port, set the output latch (p90 through p97) to 0, and read the port read (plr90 through plr97). on-chip pull-down resistors can be connected in 1-bit units with the mask option. the m PD78F0228 has no pull-down resistor. in addition, fip controller/driver output is provided as an alternate function. reset input sets port 9 to input mode. figure 4-11 shows a block diagram of port 9. figure 4-11. p90 to p97 block diagram rd : port 9 read signal wr : port 9 write signal internal bus output latch (p90-p97) wr port port read (plr90-plr97) rd mask option p90/fip32- p97/fip39 alternate function mask rom model only. PD78F0228 has no pull-down resistor. m v load
chapter 4 port functions 62 4.2.10 port 10 port 10 is an 8-bit output only port. on-chip pull-down resistors can be connected in 1-bit units with the mask option in case of mask rom model. the m PD78F0228 has no pull-down resistor. in addition, fip controller/driver segment/digit output is provided as an alternate function. figure 4-12 shows a block diagram of port 10. figure 4-12. p100 to p107 block diagram wr: port 10 write signal internal bus output latch (p100 to p107) wr port alternate function mask option p100/fip40- p107/fip47 p-ch open-drain mask rom model only. PD78F0228 has no pull-down resistor. m v load
chapter 4 port functions 63 4.3 port function control registers the following two types of registers control the ports. ? port mode registers (pm0, pm2, pm4 to pm6) ? pull-up resistor option register (pu0, pu2, pu4) (1) port mode registers (pm0, pm2, pm4 to pm6) these registers are used to set port input/output in 1-bit units. pm0, pm2 and pm4 to pm6 are independently set with a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to ffh. when a port pin is used as its alternate function pin, set the port mode register and the output latch according to table 4-3. cautions 1. pins p10 to p17 are input-only pins. 2. pins p100 to p107 are output-only pins. 3. as port 0 has an alternate function as external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. when the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. table 4-3. port mode register and output latch setting when alternate function is used pin name alternate function pmxx pxx pin name alternate function pmxx pxx function name input/output function name input/output p00 intp0 input 1 p23 ti1 input 1 p01 intp1 input 1 p24 tio50 input 1 p20 sck i/o note 1 output 0 0 p21 so output 0 0 p25 tio51 input 1 p22 si input 1 0 output 0 0 note the setting of pmxx varies depending on the clock selected by bits 1 and 0 (scl31 and scl30) of the serial operation mode register (csim3). internal clock (scl31, scl30 ? 00): 0 external clock (scl31, scl30 = 00): 1 remark : dont care pmxx: port mode register pxx : port output latch
chapter 4 port functions 64 figure 4-13. port mode register format pm0 pm2 pm47 1 111 11 pm01 pm00 76 54321 0 symbol 1 pm25 pm24 pm23 pm22 pm21 pm46 pm45 pm44 pm43 pm42 pm41 1 pm4 pm20 pm40 pmmn pmn pin input/output mode selection (m = 0: n = 0, 1) (m = 2: n = 0-5) (m = 4-6: n = 0-7) 0 1 output mode (output buffer on) input mode (output buffer off) ff20h ff22h ff24h ffh ffh ffh r/w r/w r/w address at reset r/w pm57 pm52 pm51 pm56 pm55 pm54 pm53 pm50 pm5 ff25h ffh r/w pm67 pm66 pm65 pm64 pm63 pm62 pm61 pm60 pm6 ff26h ffh r/w
chapter 4 port functions 65 (2) pull-up resistor option registers (pu0, pu2, pu4) this register is used to set whether or not to use an internal pull-up resistor of pins at ports 0, 2, 4 in 1-bit units. a pull-up resistor is internally used at bits which are set to the input mode at a bit where on-chip pull-up resistor use has been specified with pu0, pu2, and pu4. no on-chip pull-up resistors can be used to the bits set to the output mode irrespective of pu0, pu2, pu4 setting. pu0, pu2, and pu4 are set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 4-14. pull-up resistor option register format 0 0 0 0 0 0 pu01 76543210 pu0 symbol f f 3 0 h address 0 0 h at reset r/w r/w 0 0 pu25 pu24 pu23 pu22 pu21 pu20 pu2 f f 3 2 h 0 0 h r/w pu47 pu46 pu45 pu44 pu43 pu42 pu41 pu40 pu4 f f 3 4 h 0 0 h r/w pumn pu00 0 1 pmn internal pull-up resistor selection (m = 0 : n = 0, 1) (m = 2 : n = 0-5) (m = 4 : n = 0-7) internal pull-up resistor not used internal pull-up resistor used
chapter 4 port functions 66 4.4 port function operations port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 writing to input/output port (1) output mode a value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is retained until data is written to the output latch again. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined except for the manipulated bit. 4.4.2 reading from input/output port (1) output mode the output latch contents are read by a transfer instruction. the output latch contents do not change. (2) input mode the pin status is read by a transfer instruction. the output latch contents do not change. 4.4.3 operations on input/output port (1) output mode an operation is performed on the output latch contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode the output latch contents are undefined, but since the output buffer is off, the pin status does not change. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined except for the manipulated bit.
chapter 4 port functions 67 4.5 selecting mask option the mask rom models have the following mask options. the m PD78F0228 does not have mask options. table 4-4. comparison between mask options of mask rom models and m m m m m PD78F0228 pin name mask option of mask rom model m PD78F0228 p50-p57, pull-up resistor can be connected pull-up resistor is not provided. p60-p67 in 1-bit units. p70/fip16-p77/fip23, pull-down resistor can be connected pull-down resistor is not provided. p80/fip24-p87/fip31, in 1-bit units. p90/fip32-p97/fip39, p100/fip40-p107/fip47
chapter 4 port functions 68 [memo]
chapter 5 clock generator 69 chapter 5 clock generator 5.1 clock generator functions the clock generator generates clock to be supplied to the cpu and peripheral hardware. the following type of system clock oscillators is available. ? main system clock oscillator this circuit oscillates at frequencies of 5.0 mhz. oscillation can be stopped by executing the stop instruction. 5.2 clock generator configuration the clock generator consists of the following hardware. table 5-1. clock generator configuration item configuration control register processor clock control register (pcc) oscillator main system clock oscillator figure 5-1. clock generation circuit block diagram clock to peripheral hardware cpu clock (f cpu ) prescaler standby control circuit prescaler 3 processor clock control register internal bus main system clock oscillation circuit x2 x1 stop f x f x f x 2 f x 2 2 f x 2 3 f x 2 4 pcc2 pcc1 pcc0 selector selector
chapter 5 clock generator 70 5.3 register controlling clock generation circuit the clock generation circuit is controlled by the processor clock control register (pcc). ? processor clock control register (pcc) this register selects a cpu clock and selects a division ratio. pcc is set by using a 1-bit or 8-bit memory manipulation instruction. its value is set to 04h at reset. figure 5-2. processor clock control register format pcc2 pcc1 pcc0 selects cpu clock (f cpu ) 000f x 001f x /2 010f x /2 2 011f x /2 3 100f x /2 4 others setting prohibited caution be sure to clear bits 3 through 7 to 0. remark f x : oscillation frequency of main system clock the shortest instruction of the m pd780228 subseries is executed in two cpu clocks. therefore, the relation between the cpu clock (f cpu ) and minimum instruction execution time is as shown in table 5-2. table 5-2. relation between cpu clock and minimum instruction execution time cpu clock (f cpu ) minimum instruction execution time: 2/f cpu f x 0.4 m s f x /2 0.8 m s f x /2 2 1.6 m s f x /2 3 3.2 m s f x /2 4 6.4 m s f x = 5.0 mhz f x : main system clock oscillation frequency 7 0 6 0 5 0 4 0 3 0 2 pcc2 1 pcc1 0 pcc0 symbol pcc address fffbh at reset 04h r/w r/w
chapter 5 clock generator 71 5.4 system clock oscillator 5.4.1 main system clock oscillator the main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (5.0 mhz typ.) connected to the x1 and x2 pins. external clocks can be input to the main system clock oscillator. in this case, input a clock signal to the x1 pin and an antiphase clock signal to the x2 pin. figure 5-3 shows an external circuit of the main system clock oscillator. figure 5-3. external circuit of main system clock oscillator (a) crystal or ceramic oscillation (b) external clock cautions 1. the stop mode cannot be set when the external clock is input. this is because the x2 pin is pulled up by v dd1 . 2. when using a main system clock oscillator, carry out wiring in the broken line area in figure 5-3 as follows to prevent any effects from wiring capacities. ? minimize the wiring length. ? do not allow wiring to intersect with other signal conductors. do not allow wiring to come near abruptly changing high current. ? set the potential of the grounding position of the oscillator capacitor to that of v ss1 . do not ground to any ground pattern where high current is present. ? do not fetch signals from the oscillator. figure 5-4 shows examples of resonator having bad connection. crystal or ceramic resonator x2 x1 v ss1 external clock x2 x1 pd74hcu04 m
chapter 5 clock generator 72 figure 5-4. examples of resonator with bad connection (1/2) (a) too long wiring of connected circuit (b) crossed signal lines (c) high alternating current close to (d) current flowing through ground line signal lines of oscillator circuit (potentials at points a, b, and c change) x2 x1 v ss1 portn (n = 0-2, 4-10) x2 x1 v ss1 v ss1 x1 x2 high current x2 x1 v ss1 c b a pmn v dd0 high current
chapter 5 clock generator 73 figure 5-4. examples of resonator with bad connection (2/2) (e) signal extracted 5.4.2 divider the divider divides the main system clock oscillator output (f x ) and generates various clocks. v ss x1 x2
chapter 5 clock generator 74 5.5 clock generator operations the clock generator generates the following various types of clocks and controls the cpu operating mode including the standby mode. ? main system clock f x ? cpu clock f cpu ? clock to peripheral hardware the function and operation of the clock generator circuit are determined by the processor clock control register (pcc) as follows: (a) upon generation of reset signal, the lowest speed mode of the main system clock (6.4 m s when operated at 5.0 mhz) is selected (pcc = 04h). main system clock oscillation stops while low level is applied to reset pin. (b) one of the five (0.4 m s, 0.8 m s, 1.6 m s, 3.2 m s, and 6.4 m s: when operated at 5.0 mhz) cpu clock stages can be selected by setting the pcc. (c) two standby modes, the stop and halt modes, are available. (d) the main system clock is divided and supplied to the peripheral hardware. therefore, the peripheral hardware also stops if the main system clock is stopped. (except external input clock operation)
chapter 5 clock generator 75 5.6 changing cpu clock 5.6.1 time required to change cpu clock the cpu clock can be changed by using bits 0 through 2 (pcc0 through pcc2) of the processor clock control register (pcc). actually, the clock is not changed immediately after pcc has been rewritten, and the cpu operates with the old clock until the specified number of instructions (refer to table 5-3 ) has been executed after pcc was changed. table 5-3. maximum time required for changing cpu clock set value before change set value after change pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 000001010011100 0 0 0 16 instructions 16 instructions 16 instructions 16 instructions 0 0 1 8 instructions 8 instructions 8 instructions 8 instructions 0 1 0 4 instructions 4 instructions 4 instructions 4 instructions 0 1 1 2 instructions 2 instructions 2 instructions 2 instructions 1 0 0 1 instruction 1 instruction 1 instruction 1 instruction remark the time required to execute one instruction is equal to the minimum instruction execution time with the cpu clock before change.
chapter 5 clock generator 76 5.6.2 cpu clock changing procedure the cpu clock is changed in the following procedure. figure 5-5. changing cpu clock (1) the cpu is reset if the reset pin is made low after power application. the reset is cleared and the main system clock starts oscillating if the reset pin is later made high. at this time, it is automatically ensured that oscillation stabilization time (2 16 /f x ) elapses. after that, the cpu starts executing instructions at the slowest speed of the main system clock (6.4 m s at 5.0 mhz). (2) after sufficient time has elapsed during which the v dd voltage rises to the level at which the cpu can operate at the highest speed, the contents of the processor clock control register (pcc) are rewritten, and the cpu operates at the highest speed. internal reset operation wait (13.1 ms at 5.0 mhz) fastest operation slowest operation cpu clock reset v dd
chapter 6 8-bit remote control timer 77 chapter 6 8-bit remote control timer 6.1 function of 8-bit remote control timer the 8-bit remote control timer has a pulse width measurement function with a resolution of 8 bits. pulse width is measured from a difference in count value when the valid edge has been detected while the timer operates in the free-running mode. 6.2 configuration of 8-bit remote control timer the 8-bit remote control timer consists of the following hardware: table 6-1. 8-bit remote control timer configuration item configuration timer register 8-bit timer (tm1) register 8-bit capture register: 2 (cp10 and cp11) control register timer mode control register 1 (tmc1) figure 6-1. block diagram of 8-bit remote control timer inttm10 clear ti1/p23 8-bit timer (tm1) ovf 8-bit capture register (cp11) internal bus 8-bit capture register (cp10) inttm11 timer mode control register 1 1/2 internal bus noise rejection rising edge detection tce1 ovf1 tcl2 tcl1 f x /2 2 f x /2 3 f x /2 8 f x /2 9 selector noise rejection falling edge detection
chapter 6 8-bit remote control timer 78 6.3 registers controlling 8-bit remote control timer the following three types of registers control the 8-bit remote control timer. ? timer mode control register 1 (tmc1) ? 8-bit capture registers (cp10 and cp11) ? 8-bit timer register (tm1) (1) timer mode control register 1 (tmc1) this register enables or disables the operation of the 8-bit timer (tm1), sets the count clock, and detects overflow. tmc1 is set by using a 1-bit or 8-bit memory manipulation instruction. this register is initialized to 00h by reset input. figure 6-2. timer mode control register 1 format tce1 controls count operation of tm1 0 clears count to 0 and stops operation 1 starts count operation ovf1 detects overflow of tm1 0 no overflow 1 overflow tcl2 tcl1 selects count clock 00f x /2 10 (4.9 khz) 01f x /2 9 (9.8 khz) 10f x /2 4 (313 khz) 11f x /2 3 (625 khz) caution be sure to clear bits 3 through 6 to 0. remarks 1. f x : main system clock oscillation frequency 2. ( ): f x = 5.0 mhz < 7 > 0 6 0 5 0 4 0 3 0 < 2 > ovf1 1 tcl2 0 tcl1 symbol tmc1 address ff60h at reset 00h r/w r/w
chapter 6 8-bit remote control timer 79 (2) 8-bit capture registers (cp10 and cp11) these 8-bit registers capture the contents of the 8-bit timer (tm1). the capture operation is performed in synchronization with the valid edge input to the ti1 pin (capture trigger). the contents of cp10 are retained until the next rising edge of the ti1 pin is detected. the contents of cp11 are retained until the next falling edge of the ti1 pin is detected. cp10 and cp11 can be read by using an 8-bit memory manipulation instruction. the values of these registers are initialized to 00h by reset input. (3) 8-bit timer register (tm1) this 8-bit register counts the count pulse. it can be read by using an 8-bit memory manipulation instruction. the value of this register is initialized to 00h by reset input or by clearing the tce1 bit.
chapter 6 8-bit remote control timer 80 6.4 operation of 8-bit remote control timer the 8-bit remote control timer operates as a pulse width measuring circuit. the width of a high-level or low-level external pulse input to the ti1 pin is measured by operating the 8-bit timer (tm1) in the free-running mode. detection of the valid edge is sampled every 2 cycles of the count clock selected by tcl1 and tcl2, and the capture operation is not performed until the valid level has been detected two times. therefore, the pulse width input to the ti1 pin must be 5 or more of the count clock set by tcl1 and tcl2, regardless of whether the level is high or low. if the pulse width is less than 5 clocks, it cannot be detected, and the capture operation is not performed. the value of timer register 1 (tm1) is loaded to and retained in the capture registers (cp10 and cp11) in synchronization with the valid edge of the pulse input to the ti1 pin, as shown in figure 6-3. figure 6-3 shows the timing of pulse width measurement. figure 6-3. timing of pulse width measurement (1/2) (1) to measure pulse width in synchronization with rising edge ffh ffh 0h ti1 inttm10 cp10 ovf1 count starts tce = 1 capture capture 00h d0 d1 d2 d3 t0 t1 cleared by software d0 d1 d2 d3 count value of tm1 capture capture remark t0 = (d1 C d0) 1/f count t1 = (100h C d1 + d2) 1/f count f count : count clock frequency set by tcl1 and tcl2
chapter 6 8-bit remote control timer 81 figure 6-3. timing of pulse width measurement (2/2) (2) measure pulse width in synchronization with both rising and falling edges ffh ffh 0h ti1 inttm10 cp11 ovf1 count starts tce = 1 00h d1 d3 t0 t1 cleared by software d0 d1 d2 d3 cp10 00h d0 d2 inttm11 capture capture capture capture count value of tm1 remark t0 = (d1 C d0) 1/f count t1 = (100h C d2 + d3) 1/f count f count : count clock frequency set by tcl1 and tcl2
chapter 6 8-bit remote control timer 82 [memo]
chapter 7 8-bit pwm timers 83 chapter 7 8-bit pwm timers 7.1 functions of 8-bit pwm timers the 8-bit pwm timers have the following two operation modes: ? mode in which only an 8-bit timer (tm5n: n = 0 or 1) is used (single mode) ? mode in which the two 8-bit pwm timers are cascaded (16-bit resolution: cascade mode) these two modes are explained next. (1) mode in which only a tm5n (n = 0 or 1) is used (single mode) in this mode, the 8-bit pwm timer operates as an 8-bit timer/event counter. in this mode, the following functions can be used. ? interval timer ? external event counter ? square wave output ? pwm output (2) mode in which two timers are cascaded (16-bit resolution: cascade mode) when the two pwm timers are cascaded, they operate as a 16-bit timer/event counter. in this mode, the following functions can be used. ? interval timer with 16-bit resolution ? external event counter with 16-bit resolution ? square output with 16-bit resolution
chapter 7 8-bit pwm timers 84 7.2 configuration of 8-bit pwm timers the 8-bit pwm timers consist of the following hardware: table 7-1. configuration of 8-bit pwm timers item configuration timer register 8-bit counter 5n (tm5n) register 8-bit compare register 5n (cr5n) timer output tio5n control registers timer clock select register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) n = 0, 1 figure 7-1. 8-bit pwm timers block diagram inttm5n clear ovf 8-bit timer mode control register 5n internal bus f x /2 2 f x /2 6 f x /2 8 f x /2 10 8-bit counter 5n (tm5n) selector internal bus f x f x /2 4 tio50/p24, tio51/p25 selector timer clock select register 5n tio50/p24, tio51/p25 level inversion s r r s inv q 8-bit compare register 5n (cr5n) coincidence tcl5n2 tcl5n1 tcl5n0 tce5n tmc5n6 tmc5n4 lvs5n lvr5n tmc5n1 toe5n mask circuit selector selector n = 0 or 1
chapter 7 8-bit pwm timers 85 (1) 8-bit counter 5n (tm5n: n = 0 or 1) tm5n is an 8-bit read-only register that counts the count pulse. the value of this counter is incremented in synchronization with the rising edge of the count clock. when the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. the count value is cleared to 00h in the following cases. <1> reset input <2> clearing tce5n <3> coincidence between tm5n and cr5n in clear & start mode caution in the cascade mode, tce5n of the low-order timer is 00h even if it is cleared. remark n = 0 or 1 (2) 8-bit compare register 5n (cr5n: n = 0 or 1) the value set in this register is constantly compared with the count value of the 8-bit counter 5n (tm5n). when the two values coincide, an interrupt request (inttm5n) is generated (in the modes other than pwm mode). the value of cr5n can be set in a range of 00h to ffh, and can be rewritten during count operation. caution when setting data to this register in the cascade mode, be sure to stop the timer operation. remark n = 0 or 1
chapter 7 8-bit pwm timers 86 7.3 registers controlling 8-bit pwm timers the following two types of registers control the 8-bit pwm timers. ? timer clock select register 5n (tcl5n: n = 0 or 1) ? 8-bit timer mode control register 5n (tmc5n: n = 0 or 1) (1) timer clock select register 5n (tcl5n: n = 0 or 1) this register sets the count clock of the 8-bit counter 5n (tm5n: n = 0 or 1). tcl5n is set by using an 8-bit memory manipulation instruction. the value of this register is initialized to 00h by reset input. figure 7-2. format of timer clock select register tcl5n2 tcl5n1 tcl5n0 selects count clock 0 0 0 falling edge of tio5n 0 0 1 rising edge of tio5n 010f x (5.0 mhz) 011f x /2 2 (1.25 mhz) 100f x /2 4 (313 khz) 101f x /2 6 (78.1 khz) 110f x /2 8 (19.5 khz) 111f x /2 10 (4.9 khz) cautions 1. when rewriting the data of tcl5n, once stop the timer operation. 2. be sure to clear bits 3 through 7 to 0. remarks 1. the setting by tcl5n2 through tcl5n0, except that for the low-order timer, is invalid in the cascade mode. 2. n = 0 or 1 3. f x : main system clock oscillation frequency 4. ( ): f x = 5.0 mhz 7 0 6 0 5 0 4 0 3 0 2 tcl5n2 1 tcl5n1 0 tcl5n0 symbol tcl5n address ff71h(tcl50), at reset 00h r/w r/w ff79h(tcl51)
chapter 7 8-bit pwm timers 87 (2) 8-bit timer mode control register 5n (tmc5n: n = 0 or 1) tmc5n sets has the following six functions: <1> controls count operation of 8-bit counter 5n (tm5n: n = 0 or 1) <2> selects operation mode of 8-bit counter 5n (tm5n: n = 0 or 1) <3> selects single or cascade mode <4> sets status of timer output f/f (flip-flop) <5> controls timer f/f or selects active level in pwm (free-running) mode <6> controls timer output tmc5n is set by using a 1-bit or 8-bit memory manipulation instruction. this register is set to 04h by reset input.
chapter 7 8-bit pwm timers 88 figure 7-3. format of 8-bit timer control register 5n tce5n controls counting by tm5n 0 clears counter to 0 and disables counting (prescaler disabled) 1 starts counting tmc5n6 selects operation mode of tm5n 0 clear & start on coincidence between tm5n and cr5n 1 pwm (free-running) mode tmc5n4 selects single or cascade mode 0 single mode (used as low-order timer) 1 cascade mode (connected to low-order timer) lvs5n lvr5n sets status of timer output f/f 0 0 does not affect 0 1 resets timer output f/f to 0 1 0 sets timer output f/f to 1 1 1 setting prohibited tmc5n1 other than pwm mode (tmc5n6 = 0) pwm mode (tmc5n6 = 1) controls timer f/f selects active level 0 disables inversion high active 1 enables inversion low active toe5n controls timer output 0 disables output (port mode) 1 enables output remarks 1. in the pwm mode, the pwm output is at the inactive level if tce5n = 0. 2. when lvs5n and lvr5n are read after data has been set, they are 0. 3. n = 0 or 1 < 7 > tce5n 6 tmc5n6 5 0 4 tmc5n4 < 3 > lvs5n < 2 > lvr5n 1 tmc5n1 0 toe5n symbol tmc5n address ff70h(tmc50), at reset 04h r/w r/w ff78h(tmc51)
chapter 7 8-bit pwm timers 89 7.4 operations of 8-bit pwm timers 7.4.1 operation as interval timer (8-bit operation) an 8-bit pwm timer operates as an interval timer that generates an interrupt request at intervals specified by the count value set to the 8-bit compare register 5n (cr5n) in advance. when the count value of the 8-bit counter 5n (tm5n) coincides with the set value of cr5n, the value of tm5n is cleared to 0 and tm5n continues counting. at the same time, an interrupt request signal (inttm5n) is generated. the count clock of tm5n can be selected by using the bits 0 through 2 (tcl5n0 through tcl5n2) of the timer clock select register 5n (tcl5n). remark n = 0 or 1 [setting] (1) set the registers. ? tcl5n : selects count clock. ? cr5n : compare value ? tmc5n : selects clear & start mode in which tm5n is cleared and started when its value coincides with cr5n. (tmc5n = 0000xxx0b = dont care) (2) the count operation is started when tce5n = 1. (3) when the values of tm5n and cr5n coincide, inttm5n is generated (tm5n is cleared to 00h). (4) after that, inttm5n is generated at fixed intervals. to stop the count operation, clear tce5n = 0. remark n = 0 or 1
chapter 7 8-bit pwm timers 90 figure 7-4. timing of interval timer operation (1/3) (a) basic operation remarks 1. interval time = (n + 1) t: n = 00h to ffh 2. n = 0 or 1 (b) when cr5n = 00h t count clock tm5n count value cr5n tce5n inttm5n tio5n count starts clear clear 00h 01h n 00h 01h n 00h 01h n n n n n interrupt request accepted interrupt request accepted interval time interval time interval time t count clock tm5n cr5n tce5n inttm5n tio5n interval time 00h 00h 00h 00h 00h n = 0 or 1
chapter 7 8-bit pwm timers 91 figure 7-4. timing of interval timer operation (2/3) (c) when cr5n = ffh t count clock tm5n cr5n tce5n inttm5n tio5n 01h feh ffh 00h feh ffh 00h ffh ffh ffh interval time interrupt request accepted interrupt request accepted n = 0 or 1 (d) operation when cr5n is changed (m < n) count clock tm5n cr5n tce5n inttm5n tio5n n 00h m n ffh 00h m 00h nm change of cr5n tm5n overflows because m < n n = 0 or 1
chapter 7 8-bit pwm timers 92 figure 7-4. timing of interval timer operation (3/3) (e) operation when cr5n is changed (m > n) 7.4.2 operation as external event counter the external event counter counts the number of count clock pulses input to tio5n from an external source. each time the valid edge specified by the timer clock select register 5n (tcl5n) has been input to tio5n, the value of tm5n is incremented. the edge can be selected from rising or falling. if the measured value of tm5n coincides with the value of the 8-bit compare register 5n (cr5n), tm5n is cleared to 0 and an interrupt request signal (inttm5n) is generated. after that, inttm5n is generated each time the value of tm5n coincides with the value of cr5n. remark n = 0 or 1 figure 7-5. timing of external event counter operation (with rising edge specified) count clock tm5n cr5n tce5n inttm5n tio5n n? n n 00h 01h n m? m 00h 01h m change of cr5n n = 0 or 1 tio5n tm5n count value cr5n inttm5n 00h 01h 02h 03h 04h 05h n? n 00h 01h 02h 03h n n = 0 or 1
chapter 7 8-bit pwm timers 93 7.4.3 square wave (8-bit resolution) output operation a square wave of any frequency can be output at intervals specified by the value set in advance to the 8-bit compare register 5n (cr5n). if the bit 0 (toe5n) of the 8-bit timer mode control register 5n (tmc5n) is set to 1, the output status of tio5n is inverted at intervals specified by the count value set in advance to cr5n. in this way, a square wave of any frequency (duty = 50%) can be output. remark n = 0 or 1 [setting] (1) set each register. ? set 0 to port latch and port mode register. ? tcl5n : selects count clock. ? cr5n : compare value ? tmc5n : clear & start mode in which tm5n is cleared and started when its value coincides with that of cr5n. lvs5n lvr5n status setting of timer output f/f 1 0 high-level output 0 1 low-level output inversion of the timer output f/f is enabled. timer output enable ? toe5n = 1 (2) the count operation is started when tce5n = 1. (3) the timer output f/f is inverted when the values of tm5n and cr5n coincide. moreover, inttm5n is generated, and tm5n is cleared to 00h. (4) after that, the timer output f/f is inverted at fixed intervals, and tio5n outputs a square wave. remark n = 0 or 1
chapter 7 8-bit pwm timers 94 7.4.4 8-bit pwm output operation the pwm timer performs 8-bit pwm output operation when bit 6 of the 8-bit timer mode control register 5n (tmc5n) is set to 1, and outputs a pulse with a duty factor determined by the value set to the 8-bit compare register 5n (cr5n) from the tio5n pin. set the width of the active level of the pwm pulse to cr5n. the active level can be selected by bit 1 (tmc5n1) of tmc5n. the count clock can be selected by bits 0 through 2 (tcl5n0 through tcl5n2) of the timer clock select register 5n (tcl5n). pwm output can be enabled or disabled by bit 0 (toe5n) of tmc5n. caution cr5n can be rewritten only once in one cycle in the pwm mode. remark n = 0 or 1 (1) basic pwm output operation [setting] (1) set 0 to the port latch and port mode register n. (2) set the active level width by using 8-bit compare register 5n (cr5n). (3) select the count clock by using timer clock select register 5n (tcl5n). (4) select the active level by using bit 1 (tmc5n1) of tmc5n. (5) the timer starts counting when bit 7 (tce5n) of tmc5n is set to 1. to stop the counting, set 0 to tce5n. remark n = 0 or 1 [pwm output operation] (1) when the timer starts counting, an inactive level is output from tio5n as pwm output, until the timer overflows. (2) when the overflow occurs, the active level set in (1) in [setting] above is output. the active level is continuously output until the cr5n and the count value of the 8-bit counter 5n (tm5n) coincide. (3) the inactive level is output after cr5n and the count value have coincided, until an overflow occurs again. (4) after that, (2) and (3) are repeated, until the counting operation is stopped. (5) pwm output is deasserted inactive when the counting operation is stopped by clearing tce5n to 0. remark n = 0 or 1
chapter 7 8-bit pwm timers 95 (a) basic pwm output operation figure 7-6. pwm output operation timing (i) basic operation (when active level = h) count clock tm5n cr5n tce5n inttm5n tio5n 00h 01h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h n active level inactive level active level n = 0 or 1 tm5n cr5n tce5n inttm5n tio5n 01h 00h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h ffh n+2 inactive level active level inactive level active level inactive level n = 0 or 1 (iii) when cr5n = ffh count clock tm5n cr5n tce5n inttm5n tio5n inactive level inactive level 01h 00h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h 00h n+2 n = 0 or 1 (ii) when cr5n = 0
chapter 7 8-bit pwm timers 96 (b) operation when cr5n is changed figure 7-7. operation timing when cr5n is changed (i) if cr5n value is changed from n to m before overflow of tm5n (iii) if cr5n value is changed from n to m for duration of 2 clocks (00h and 01h) immediately after overflow of tm5n count clock tm5n cr5n tce5n inttm5n tio5n n n+1 n+2 ffh 00h 01h n n+1 n+2 ffh 00h 01h 02h n 02h n h 03h m m m+1 m+2 cr5n changed (n ? m) n = 0 or 1 (ii) if cr5n value is changed from n to m after overflow of tm5n count clock tm5n cr5n tce5n inttm5n tio5n cr5n changed (n ? m) n n+1 n+2 ffh 00h 01h m m+1 m+2 ffh 00h 01h 02h m m+1 m+2 n 02h m h n = 0 or 1 count clock tm5n cr5n tce5n inttm5n tio5n n n+1 n+2 ffh 00h 01h n n+1 n+2 ffh 00h 01h 02h n 02h n h m m m+1 m+2 cr5n changed (n ? m) n = 0 or 1
chapter 7 8-bit pwm timers 97 (2) cascade (16-bit timer) mode ? operation as interval timer (with 16-bit resolution) the two pwm timers can be used as a 16-bit timer/counter by setting bit 4 (tmc5n4) of the 8-bit timer mode control register 5n (tmc5n) to 1. in this case, the 16-bit timer/counter operates as an interval timer that repeatedly generates an interrupt request at intervals specified by the count value set in advance to the 8-bit compare register 5n (cr5n). remark n = 0 or 1 [setting] (1) set each register. ? tcl5n : the low-order timer selects the count clock. the setting of the high-order cascaded timer is not necessary. ? cr5n : compare value (each compare value can be set in a range of 00h to ffh.) ? tmc5n : selects the clear & start mode in which the timers are cleared and started on coincidence between tm5n and cr5n. low-order timer ? tmc5n = 0000 0b : dont care high-order timer ? tmc5n = 0001 0b : dont care (2) the counting is started when tce5n of the high-order timer is set to 1 followed by setting of tce5n of the low-order timer to 1. (3) when the values of tm5n and cr5n of the cascaded timers cascade coincide, inttm5n is generated by the low-order timer (all the tm5ns are cleared to 00h). (4) after that, inttm5n is repeatedly generated at the same interval. cautions 1. before setting the 8-bit compare register 5n (cr5n), be sure to stop the timer operation. 2. even when the timers are cascaded, if the count value of the high-order timer coincides with the value of cr5n, intt5n of the high-order timer is generated, unless masked. be sure to mask and disable the interrupt of the high-order timer. 3. set tce5n of the high-order timer first, and then that of the low-order timer. 4. the counting can be restarted or stopped by setting 1 or 0 to tce5n of only the low- order timer. remark n = 0 or 1
chapter 7 8-bit pwm timers 98 figure 7-8 shows an example of the timing in the 16-bit resolution cascade mode. figure 7-8. 16-bit resolution cascade mode count clock tm50 tm51 cr50 cr51 tce50 tce51 inttm50 tio50 operation enabled count starts interval time 00h 01h n n+1 ffh 00h ffh 00h ffh 00h 01h n 00h 01h a 00h 00h 01h 02h m? m 00h b 00h n m interrupt request generated level inverted counter cleared operation stopped
chapter 7 8-bit pwm timers 99 7.5 notes on 8-bit pwm timers (1) error on starting timer the time until the coincidence signal is generated after the timer has been started includes an error of up to 1 clock, because the 8-bit counter n (tm5n: n = 0 or 1) is started in asynchronization with the count pulse. figure 7-9. start timing of 8-bit counter 5n (tm5n) 00h 01h 02h 03h 04h - timer starts count pulse tm5n count value n = 0 or 1 (2) operation after changing compare register during timer count operation if the value to which the current value of the 8-bit compare register 5n (cr5n) is changed is less than the value of the 8-bit timer register 5n, the timer continues counting, overflows, and restarts counting from 0. if the new value of cr5n (m) is less than the old value (n), the timer must be restarted after cr5n has been changed. remark n = 0 or 1 figure 7-10. timing after changing compare register value during timer count operation count pulse cr5n tm5n count value nm x? x ffh 00h 01h 02h n > x > m n = 0 or 1 caution except when tio5n input is selected, be sure to clear tce5n to 0 to set the stop status (n = 0 or 1). (3) reading tm5n during timer operation because the selected clock is temporarily stopped when tm5n (n = 0 or 1) is read during operation, select a clock with a long high/low level.
chapter 7 8-bit pwm timers 100 [memo]
chapter 8 watchdog timer 101 chapter 8 watchdog timer 8.1 function of watchdog timer the watchdog timer has the following functions: ? watchdog timer ? interval timer ? selection of oscillation stabilization time caution select whether the watchdog timer is used in the watchdog timer mode or interval timer mode, by using the watchdog timer mode register (wdtm). (1) watchdog timer mode in this mode, the watchdog timer detects a program hang-up. on detection of hang-up, the non-maskable interrupt or reset signal can be generated. table 8-1. hang-up detection time of watchdog timer hang-up detection time f x = 5.0 mhz hang-up detection time f x = 5.0 mhz 2 12 1/f x 819 m s2 16 1/f x 13.1 ms 2 13 1/f x 1.64 ms 2 17 1/f x 26.2 ms 2 14 1/f x 3.28 ms 2 18 1/f x 52.4 ms 2 15 1/f x 6.55 ms 2 20 1/f x 210 ms f x : main system clock oscillation frequency (2) interval timer mode in this mode, the watchdog timer generates an interrupt request at fixed time intervals. table 8-2. interval time interval time f x = 5.0 mhz interval time f x = 5.0 mhz 2 12 1/f x 819 m s2 16 1/f x 13.1 ms 2 13 1/f x 1.64 ms 2 17 1/f x 26.2 ms 2 14 1/f x 3.28 ms 2 18 1/f x 52.4 ms 2 15 1/f x 6.55 ms 2 20 1/f x 210 ms f x : main system clock oscillation frequency
chapter 8 watchdog timer 102 8.2 configuration of watchdog timer the watchdog timer consists of the following hardware. table 8-3. configuration of watchdog timer item configuration control register oscillation stabilization time select register (osts) watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) figure 8-1. watchdog timer block diagram f x f x /2 7 run clock input control circuit divider divided clock select circuit output control circuit intwdt reset wdt mode signal 3 divided mode select circuit internal bus watchdog timer clock select register oscillation stabilization time select register watchdog timer mode register osts2 osts1 osts0 wdcs2 wdcs1 wdcs0 wdtm4 wdtm3 run
chapter 8 watchdog timer 103 8.3 registers controlling watchdog timer the following three types of registers control the watchdog timer. ? oscillation stabilization time select register (osts) ? watchdog timer clock select register (wdcs) ? watchdog timer mode register (wdtm) (1) oscillation stabilization time select register (osts) this register selects the oscillation stabilization time during which oscillation is stabilized after the reset signal has been deasserted or the stop mode has been released. this register is set by using a 1-bit or 8-bit memory manipulation instruction. its value is set to 04h by reset input. figure 8-2. oscillation stabilization time select register format osts2 osts1 osts0 selects oscillation stabilization time at stop mode release 0002 11 /f x (410 m s) 0012 13 /f x (1.64 ms) 0102 14 /f x (3.28 ms) 0112 15 /f x (6.55 ms) 1002 16 /f x (13.1 ms) others setting prohibited remarks 1. f x : main system clock oscillation frequency 2. ( ): f x = 5.0 mhz 7 0 6 0 5 0 4 0 3 0 2 osts2 1 osts1 0 osts0 symbol osts address fffah at reset 04h r/w r/w
chapter 8 watchdog timer 104 (2) watchdog timer clock select register (wdcs) this register selects the overflow time of the watchdog timer or interval timer. it is set by using an 8-bit manipulation instruction. the value of this register is initialized to 00h by reset input. figure 8-3. watchdog timer clock select register format wdcs2 wdcs1 wdcs0 overflow time of watchdog timer/interval timer 0002 12 /f x (819 m s) 0012 13 /f x (1.64 ms) 0102 14 /f x (3.28 ms) 0112 15 /f x (6.55 ms) 1002 16 /f x (13.1 ms) 1012 17 /f x (26.2 ms) 1102 18 /f x (52.4 ms) 1112 20 /f x (210 ms) remarks 1. f x : main system clock oscillation frequency 2. ( ): f x = 5.0 mhz 7 0 6 0 5 0 4 0 3 0 2 wdcs2 1 wdcs1 0 wdcs0 symbol wdcs address ff42h at reset 00h r/w r/w
chapter 8 watchdog timer 105 (3) watchdog timer mode register (wdtm) this register selects the operation mode of the watchdog timer, and enables or disables the counting operation. it is set by using a 1-bit or 8-bit memory manipulation instruction. the value of this register is initialized to 00h by reset input. figure 8-4. watchdog timer mode register format run selects operation of watchdog timer note 1 0 stops counting 1 clears counter and starts counting wdtm4 wdtm3 selects operation mode of watchdog timer note 2 0 interval timer mode (maskable interrupt request occurs when overflow occurs.) 1 0 watchdog timer mode 1 (non-maskable interrupt request occurs when overflow occurs.) 1 1 watchdog timer mode 2 (reset operation is started when overflow occurs.) notes 1. the run bit cannot be cleared to 0 by software once it has been set. therefore, counting cannot be stopped, after it has been started, by any means other than reset input. 2. the wdtm3 and wdtm4 bits cannot be cleared to 0 by software once they have been set. caution when the run bit is set to 1 and the watchdog timer is cleared, the actual overflow time is up to 0.5% shorter than the set time. remark : dont care < 7 > run 6 0 5 0 4 wdtm4 3 wdtm3 2 0 1 0 0 0 symbol wdtm address fff9h at reset 00h r/w r/w
chapter 8 watchdog timer 106 8.4 operation of watchdog timer 8.4.1 operation as watchdog timer the watchdog timer operates to detect a program hang-up when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1. the count clock of the watchdog timer (hang-up detection time interval) can be selected by bits 0 through 2 (wdcs0 through wdcs2) of the watchdog timer clock select register (wdcs). by setting bit 7 (run) of wdtm, the watchdog timer starts the count operation. if run is set to 1 again within the specified hang-up detection time interval after the counting operation has been started, the watchdog timer is cleared, and starts the count operation again. if run is not set to 1 and the hang-up detection time is exceeded, the system is reset or the non-maskable interrupt request is generated, depending on the value of bit 3 (wdtm3) of wdtm. the watchdog timer continues its operation in the halt mode, but stops in the stop mode. therefore, set run to 1 and clear the watchdog timer before executing the stop instruction to set the stop mode. caution the actual hang-up detection time may be up to 0.5% shorter than the set time. table 8-4. hang-up detection time of watchdog timer wdcs2 wdcs1 wdcs0 hang-up detection time of watchdog timer 0002 12 /f x (819 m s) 0012 13 /f x (1.64 ms) 0102 14 /f x (3.28 ms) 0112 15 /f x (6.55 ms) 1002 16 /f x (13.1 ms) 1012 17 /f x (26.2 ms) 1102 18 /f x (52.4 ms) 1112 20 /f x (210 ms) remarks 1. f x : main system clock oscillation frequency 2. ( ): f x = 5.0 mhz
chapter 8 watchdog timer 107 8.4.2 operation as interval timer the watchdog timer operates as an interval timer that repeatedly generates an interrupt request at intervals specified by the count value set in advance if bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is cleared to 0. the count clock (interval time) can be selected by bits 0 through 2 (wdcs0 through wdcs2) of the watchdog timer clock select register (wdcs). by setting bit 7 (run) of wdtm to 1, the watchdog timer starts interval timer operation. while the watchdog timer is operating as an interval timer, the interrupt mask flag (tmmk4) and priority specification flag (tmpr4) are valid, and a maskable interrupt (intwdt) can be generated. the default priority of intwdt is the highest of all the maskable interrupts. the interval timer continues operating in the halt mode, but stops in the stop mode. therefore, set run and clear the interval timer before executing the stop instruction to set the stop mode. cautions 1. if bit 4 (wdtm4) of wdtm has been set to 1 once (to select the watchdog timer mode), the interval timer mode cannot be set unless the reset signal is input. 2. the interval time immediately after wdtm has been set may be up to 0.5% shorter than the set time. table 8-5. interval time of interval timer wdcs2 wdcs1 wdcs0 interval time 0002 12 /f x (819 m s) 0012 13 /f x (1.64 ms) 0102 14 /f x (3.28 ms) 0112 15 /f x (6.55 ms) 1002 16 /f x (13.1 ms) 1012 17 /f x (26.2 ms) 1102 18 /f x (52.4 ms) 1112 20 /f x (210 ms) remarks 1. f x : main system clock oscillation frequency 2. ( ): f x = 5.0 mhz
chapter 8 watchdog timer 108 [memo]
chapter 9 a/d converter 109 chapter 9 a/d converter 9.1 function of a/d converter the a/d converter converts analog input signals into digital values with a resolution of 8 bits. eight analog input channels (ani0 through ani7) can be controlled. the a/d conversion operation can be started only by software. one of the analog input channels, ani0 through ani7, is selected for a/d conversion. the a/d conversion operation is repeatedly performed, and each time it has been completed once, an interrupt request (intad) is generated. 9.2 configuration of a/d converter the a/d converter consists of the following hardware: table 9-1. a/d converter configuration item configuration analog input 8 channels (ani0 through ani7) register successive approximation register (sar) a/d conversion result register (adcrh0) control register a/d converter mode register (adm0) analog input channel specification register (ads0)
chapter 9 a/d converter 110 figure 9-1. a/d converter block diagram (1) successive approximation register (sar) this register compares the voltage value of the input analog signal with the value of the voltage tap (compare voltage) from the series resistor string, and holds the result of the comparison, starting from the most significant bit (msb). when the comparison result has been retained to this register up to the least significant bit (lsb) (i.e., when the a/d conversion has been completed), the contents of this register are transferred to the a/d conversion result register (adcrh0). (2) a/d conversion result register (adcrh0) this register holds the result of the a/d conversion. each time the a/d conversion has been completed, the conversion result is loaded to this register from the successive approximation register (sar). adcrh0 is read by using an 8-bit memory manipulation instruction. the value of this register is initialized to 00h by reset input. (3) sample & hold circuit the sample & hold circuit samples the analog input signals sent from the input circuit one by one, and sends them to the voltage comparator. it also holds the voltage value of the sampled analog input signal during a/d conversion. ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 sample & hold circuit voltage comparator successive approximation register (sar) control circuit 4 a/d conversion result register (adcrh0) av dd av ss intad a/d converter mode register analog input channel specification register internal bus av ss cs0 0 fr02 fr01 fr00 0 0 0 ads03 ads02 ads01 ads00 selector tap selector
chapter 9 a/d converter 111 (4) voltage comparator the voltage comparator compares the analog input signal with the output voltage of the series resistor string. (5) series resistor string the series resistor string is connected between the av dd and av ss pins, and generates a voltage to be compared with the input analog signal. (6) ani0 through ani7 pins these are 8 channels of analog input pins of the a/d converter, and input analog signals to be converted. caution make sure that the input voltages of ani0 through ani7 are within the rated range. if a voltage greater than av dd or less than av ss is input a channel (even if it is within the absolute maximum rating range), the converted value of the channel is undefined, and, in the worst case, the converted values of the other channels are affected. (7) av ss pin this is the ground potential pin of the a/d converter. make sure this pin is always at the same potential as the v ss1 pin even when the a/d converter is not used. (8) av dd pin this is the analog power supply pin of the a/d converter. make sure that this pin is always at the same potential as the v dd1 pin even when the a/d converter is not used. in the standby mode, the current flowing to the series resistor string can be lowered by stopping the conversion operation (by clearing bit 7 (cs0) of the a/d converter mode register (adm0)).
chapter 9 a/d converter 112 9.3 registers controlling a/d converter the following two types of registers control the a/d converter. ? a/d converter mode register (adm0) ? analog input channel specification register (ads0) (1) a/d converter mode register (adm0) this register specifies the conversion time of the input analog signal to be converted, and starts or stops the conversion operation. it is set by using a 1-bit or 8-bit memory manipulation instruction. the value of this register is initialized to 00h by reset input. figure 9-2. a/d converter mode register format cs0 control a/d conversion operation 0 stops conversion 1 enables conversion fr02 fr01 fr00 selects a/d conversion time note 1 f x = 5.0 mhz f x = 4.19 mhz 0 0 0 144/f x (28.8 m s) 144/f x (34.4 m s) 0 0 1 120/f x (24 m s) 120/f x (28.6 m s) 0 1 0 96/f x (19.2 m s) 96/f x (22.9 m s) 1 0 0 72/f x (14.4 m s) 72/f x (17.2 m s) 1 0 1 60/f x (setting prohibited note 2 ) 60/f x (14.3 m s) 1 1 0 48/f x (setting prohibited note 2 ) 48/f x (setting prohibited note 2 ) others setting prohibited notes 1. make sure that the a/d conversion time is 14 m s or longer. 2. these settings are prohibited because the a/d conversion time is less than 14 m s. caution the conversion result is undefined immediately after bit 7 (cs0) has been set. remark f x : main system clock oscillation frequency < 7 > cs0 6 0 5 fr02 4 fr01 3 fr00 2 0 1 0 0 0 symbol adm0 address ff80h at reset 00h r/w r/w
chapter 9 a/d converter 113 (2) analog input channel specification register (ads0) this register specifies a port that inputs the analog voltage to be converted. it is set by using a 1-bit or 8-bit memory manipulation instruction. the value of this register is initialized to 00h by reset input. figure 9-3. analog input channel specification register format ads03 ads02 ads01 ads00 specifies analog input channel 0 0 0 0 ani0 0 0 0 1 ani1 0 0 1 0 ani2 0 0 1 1 ani3 0 1 0 0 ani4 0 1 0 1 ani5 0 1 1 0 ani6 0 1 1 1 ani7 others setting prohibited 7 0 6 0 5 0 4 0 3 ads03 2 ads02 1 ads01 0 ads00 symbol ads0 address ff81h at reset 00h r/w r/w
chapter 9 a/d converter 114 9.4 operation of a/d converter 9.4.1 basic operation of a/d converter (1) select one channel for a/d conversion by using the analog input channel specification register (ads0). (2) the sample & hold circuit samples the voltage input to the selected analog input channel. (3) the sample & hold circuit enters the hold status after it has performed sampling for fixed time, and holds the input analog voltage until the a/d conversion is completed. (4) bit 7 of the successive approximation register (sar) is set. the tap selector sets the voltage tap of the series resistor string to (1/2) av dd . (5) the voltage comparator compares the voltage difference between the voltage of the series resistor string and voltage tap. if the input analog voltage is greater than (1/2) av dd , the msb of sar remains set. if it is less than (1/2) av dd , msb is reset. (6) bit 6 of sar is automatically set, and the next comparison is performed. the voltage tap of the series resistor string is selected as follows, depending on the value of bit 7 to which the result has been already set. ? bit 7 = 1: (3/4) av dd ? bit 7 = 0: (1/4) av dd this voltage tap is compared with the input analog voltage. depending on this result, bit 6 of sar is manipulated as follows: ? if input analog voltage ? voltage tap: bit 6 = 1 ? if input analog voltage - voltage tap: bit 6 = 0 (7) comparison continues like this up to bit 0 of sar. (8) when comparison of 8 bits has been completed, the valid digital result remains in sar, and its value is transferred and latched to the a/d conversion result register (adcrh0). at the same time, an a/d conversion end interrupt request (intad) is generated.
chapter 9 a/d converter 115 figure 9-4. basic operation of a/d converter the a/d conversion operation is performed successively until bit 7 (cs0) of the a/d converter mode register (adm0) is reset to 0 by software. if an attempt is made to write data to adm0 or analog input channel specification register (ads0) during a/d conversion operation, the conversion operation is initialized, and conversion is started from the beginning if cs0 is set to 1. the value of the a/d conversion result register (adcrh0) is undefined when the reset signal is input. conversion time sampling time sampling a/d conversion undefined 80h c0h or 40h conversion result conversion result operation of a/d converter sar adcrh0 intad
chapter 9 a/d converter 116 9.4.2 input voltage and conversion result the analog voltage input to an analog input pin (ani0 to ani7) and the result of a/d conversion (a/d conversion result register (adcrh0)) have the following relation: adcrh0 = int ( v in 256 + 0.5) av dd or, (adcrh0 C 0.5) av dd - v in < (adcrh0 + 0.5) av dd 256 256 int( ) : function that returns integer of value in ( ) v in : analog input voltage av dd : supply voltage to a/d converter adcrh0 : value of a/d conversion result register (adcrh0) figure 9-5 shows the relation between the input analog voltage and a/d conversion result. figure 9-5. relation between input analog voltage and a/d conversion result 255 254 253 3 2 1 0 a/d conversion result (adcrh0) 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 input voltage/av dd
chapter 9 a/d converter 117 9.4.3 operation mode of a/d converter select one analog input channel from ani0 through ani7 by the analog input channel specification register (ads0) to start a/d conversion. the a/d conversion operation can be started only by software (by setting the a/d converter mode register (adm0)). the a/d conversion result is stored in the a/d conversion result register (adcrh0), and an interrupt request signal (intad) is generated. ? a/d conversion by software start converting the voltage applied to the analog input pin specified by the analog input channel specification register (ads0) is started when bit 7 (cs0) of the a/d converter mode register (adm0) is set to 1. when the a/d conversion has been completed, the result of the conversion is stored in the a/d conversion result register (adcrh0), and an interrupt request (intad) is generated. when the a/d conversion has been started and completed once, the next conversion operation is immediately started. this is repeated until new data is written to ads0. if ads0 is rewritten during a/d conversion, the conversion under execution is stopped, and conversion of the selected analog input channel is started. if data with cs0 being 0 is written to adm0 during a/d conversion, the conversion is immediately stopped. figure 9-6. a/d conversion by software start remark n = 0, 1, ... 7 m = 0, 1, ... 7 rewriting ads0 cs0 = 1 rewriting ads0 cs0 = 1 cs0 = 0 a/d conversion adcrh0 intad anin anin anin anim anim stop anin anin anim conversion result does not remain during a/d conversion
chapter 9 a/d converter 118 9.5 notes on a/d converter (1) current consumption in standby mode the a/d converter is stopped in the standby mode. at this time, the current consumption can be reduced by stopping the conversion (by clearing bit 7 (cs0) of the a/d converter mode register (adm0) to 0). figure 9-7 shows how the current consumption can be reduced in the standby mode. figure 9-7. example of reducing current consumption in standby mode av dd av ss p-ch series resistor string cs0 (2) input range of ani0 to ani7 make sure that the input voltages of ani0 through ani7 are within the rated range. if a voltage greater than av dd or less than av ss is input to a channel (even if it is within the absolute maximum rating range), the converted value of the channel is undefined, and, in the worst case, the converted values of the other channels are affected. (3) conflicting operation <1> conflict between writing and reading a/d conversion result register (adcrh0) on completion of conversion reading adrch0 takes precedence. after adcrh0 has been read, a new conversion result is written to adcrh0. <2> conflict between writing adcrh0 and input of external trigger signal on completion of conversion an external trigger signal is not accepted during a/d conversion. therefore, the external trigger signal is not accepted while adcrh0 is written. <3> conflict between writing adcrh0 and writing a/d converter mode register (adm0) or writing analog input channel specification register (ads0) on completion of conversion writing adm0 or ads0 takes precedence. adcrh0 is not written. nor is the conversion end interrupt request signal (intad) generated.
chapter 9 a/d converter 119 (4) noise measures to maintain the 8-bit resolution, care must be exercised that no noise is superimposed on the av dd and ani0 through ani7 pins. the higher the output impedance of the analog input source, the heavier the influence of noise. to suppress noise, connecting external c as shown in figure 9-8 is recommended. figure 9-8. processing of analog input pin (5) ani0 through ani7 the analog input pins (ani0 through ani7) are multiplexed with port pins (p10 through p17). when one of ani0 through ani7 is selected for a/d conversion, do not execute an instruction that inputs data to the port during the conversion. if such an instruction is executed, the conversion resolution may drop. when a digital pulse is applied to a pin adjacent to the analog input pins during a/d conversion, the expected a/d conversion value may not be obtained because of coupling noise. therefore, do not apply a pulse to the pins adjacent to the analog input pins during a/d conversion. (6) input impedance of av dd pin a series resistor string with a resistance of about 24.7 k w is connected between the av dd and av ss pins. if the output impedance of the reference voltage source is high, therefore, the impedance is virtually connected in parallel with the resistor string between the av dd and av ss pins, increasing the error of the reference voltage. (7) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the contents of the analog input channel specification register (ads0) are changed. if the analog input pin is changed during a/d conversion, therefore, the a/d conversion result of the old analog input may be written to ads0 immediately before ads0 is rewritten, and consequently, the conversion end interrupt flag may be set. if adif is read immediately after ads0 has been rewritten, adif may be set despite that the a/d conversion of the new analog input has not been completed. before resuming a/d conversion that has been stopped, clear adif. reference voltage input c = 100-1000 pf clamp with diode with low v f (0.3 v or less) if there is possibility that noise greater than av dd and less than av ss is superimposed. v dd1 av ss v ss1 av dd
chapter 9 a/d converter 120 figure 9-9. a/d conversion end interrupt request generation timing remark n = 0, 1, ... 7 m = 0, 1, ... 7 (8) av dd pin the av dd pin supplies power to the analog circuit. it also supplies power to the input circuit of ani0 through ani7. therefore, apply the same potential as that of the v dd1 pin to this pin, as shown in figure 9-10, in an application where a backup power supply is used. figure 9-10. processing of av dd pin main power supply backup capacitor v dd1 av dd v ss1 av ss ads0 rewriting (anin conversion starts) a/d conversion adcrh0 intad anin anin anim anin anin anim anim anim ads0 rewriting (anim conversion starts) adif is set, but conversion of anim is not completed
chapter 10 serial interface 121 chapter 10 serial interface 10.1 function of serial interface the serial interface has the following two modes. ? operation stop mode ? three-wire serial i/o mode (1) operation stop mode this mode is used when serial transfer is not performed. (2) three-wire serial i/o mode (with msb first) in this mode, 8-bit data is transferred by using three lines: serial clock (sck), serial output (so), and serial input (si). because simultaneous transmission/reception operation can be performed in the three-wire serial i/o mode, the processing time of data transfer can be shortened. the first bit of the 8-bit data to be transferred is fixed to the msb. the three-wire serial i/o mode is useful when connecting peripheral i/os or display controller having a clocked serial interface. 10.2 configuration of serial interface the serial interface consists of the following hardware. table 10-1. serial interface configuration item configuration register serial i/o shift register 3 (sio3) control register serial operation mode register 3 (csim3)
chapter 10 serial interface 122 figure 10-1. serial interface block diagram internal bus serial i/o shift register 3 (sio3) serial operation mode register 3 serial clock counter sampling circuit clock selector r qd mode0 sio3 read sio3 write intcsi3 mode0 si/p22 so/p21 sck/p20 f x /2 3 -f x /2 5 csie3 0000 mode0 scl31 scl30 (1) serial i/o shift register 3 (sio3) this 8-bit register converts parallel data to serial data to perform serial transmission/reception (shift operation) in synchronization with the serial clock. sio3 is set by using an 8-bit memory manipulation instruction. the serial operation is started by writing data to or reading data from sio3 when bit 7 (csie3) of the serial operation mode register 3 (csim3) is 1. during transmission, the data written to sio3 is output to the serial output line (so). during reception, the data is read to sio3 from the serial input line (si). the contents of this register are undefined when the reset signal is input. caution do not access sio3 during transmission, except when triggering the transmission (reading sio3 is prohibited when bit 2 (mode0) of csim3 = 0, and writing is prohibited when mode0 = 1). (2) serial clock counter this counter counts the serial clock output or input during transmission/reception to check that 8-bit data has been transmitted/received.
chapter 10 serial interface 123 10.3 registers controlling serial interface the serial interface is controlled by the serial operation mode register 3 (csim3). ? serial operation mode register 3 (csim3) this register selects the serial clock and operation mode of the serial interface, and enables or disables the operation. it is set by using a 1-bit or 8-bit memory manipulation instruction. the value of this register is initialized to 00h by reset input. figure 10-2. serial operation mode register 3 format csie3 enables or disables operation of sio3 shift register operation serial counter port 0 disabled cleared port function note 1 enabled count operation enabled serial function + port function mode0 transfer operation mode flag operation mode transfer start trigger so output 0 transmission or transmission/ sio3 write normal output reception mode 1 reception mode sio3 read fixed to low level scl31 scl30 selects clock 0 0 external clock input to sck pin 01f x /2 3 (625 khz) 10f x /2 4 (313 khz) 11f x /2 5 (156 khz) note the pins connected to si, so, and sck can be used as port pins when csie3 = 0 (when the sio3 operation is stopped). remarks 1. f x : main system clock oscillation frequency 2. ( ): f x = 5.0 mhz < 7 > csie3 6 0 5 0 4 0 3 0 2 mode0 1 scl31 0 scl30 symbol csim3 address ff86h at reset 00h r/w r/w
chapter 10 serial interface 124 10.4 operation of serial interface the serial interface operates in the following two modes: ? operation stop mode ? three-wire serial i/o mode 10.4.1 operation stop mode in the operation stop mode, the power consumption can be reduced because serial transfer is not executed. because the serial i/o shift register 3 (sio3) does not perform the shift operation, this register can be used as a normal 8-bit register. in this mode, the p20/sck, p21/so, and p22/si pins can be used as normal i/o port pins. (1) register setting the operation stop mode is set by the serial operation mode register 3 (csim3). csim3 is set by using a 1-bit or 8-bit memory manipulation instruction. the value of this register is initialized to 00h by reset input. csie3 enables or disables operation of sio3 shift register operation serial counter port 0 disabled cleared port function note 1 enabled count operation enabled serial function + port function note the pins connected to si, so, and sck can be used as port pins when csie3 = 0 (when the sio3 operation is stopped). < 7 > csie3 6 0 5 0 4 0 3 0 2 mode0 1 scl31 0 scl30 symbol csim3 address ff86h at reset 00h r/w r/w
chapter 10 serial interface 125 10.4.2 three-wire serial i/o mode the three-wire serial i/o mode is useful for connecting a peripheral i/o or display controller having a clocked serial interface. communication is established by using three lines: serial clock (sck), serial output (so), and serial input (si). (1) register setting the three-wire serial i/o mode is set by the serial operation mode register 3 (csim3). it is set by using a 1-bit or 8-bit memory manipulation instruction. the value of this register is initialized to 00h by reset input. csie3 enables or disables operation of sio3 shift register operation serial counter port 0 disabled cleared port function note 1 enabled count operation enabled serial function + port function mode0 transfer operation mode flag operation mode transfer start trigger so output 0 transmission or transmission/ sio3 write normal output reception mode 1 reception mode sio3 read fixed to low level scl31 scl30 selects clock 0 0 external clock input to sck pin 01f x /2 3 (625 khz) 10f x /2 4 (313 khz) 11f x /2 5 (156 khz) note the pins connected to si, so, and sck can be used as port pins when csie3 = 0 (when the sio3 operation is stopped). remarks 1. f x : main system clock oscillation frequency 2. ( ): f x = 5.0 mhz < 7 > csie3 6 0 5 0 4 0 3 0 2 mode0 1 scl31 0 scl30 symbol csim3 address ff86h at reset 00h r/w r/w
chapter 10 serial interface 126 (2) communication operation in the three-wire serial i/o mode, data is transmitted or received in 8-bit units. each bit of the data is transmitted or received in synchronization with the serial clock. the shift operation of the serial i/o shift register 3 (sio3) is performed in synchronization with the falling of the serial clock (sck). the transmit data is retained by the so latch and output from the so pin. at the rising edge of sck, the receive data input to the si pin is latched to sio3. when transfer of 8-bit data has been completed, sio3 automatically stops its operation, and an interrupt request flag (csiif3) is set. figure 10-3. timing in three-wire serial i/o mode sck si so csiif3 transfer is started at falling edge of sck transfer completed 12345678 di7 di6 di5 do7 do6 do5 di4 di3 di2 do4 do3 do2 di1 di0 do1 do0 (3) transfer start serial transfer is started when data is assigned to (or read from) the serial i/o shift register 3 (sio3) if the following two conditions are satisfied. ? operation control bit of sio3 (csie3) = 1 ? if the internal serial clock is stopped or sck is high after 8-bit serial transfer ? transmission or transmission/reception mode transfer is started if sio3 is written when csie3 = 1 and mode0 = 0. ? reception mode transfer is started if sio3 is read when csie3 = 1 and mode0 = 1. caution transfer is not started even if csie3 is set to 1 after data has been written to sio3. serial transfer is automatically stopped and an interrupt request flag (csiif3) is set when 8-bit transfer has been completed.
chapter 11 fip controller/driver 127 chapter 11 fip controller/driver 11.1 function of fip controller/driver the fip controller/driver of the m pd780228 subseries has the following functions. (1) can output display signals (dma operation) by automatically reading display data. (2) the pins not used for fip display can be used as i/o port or output port pins (fip16 through fip47 pins only). (3) luminance can be adjusted in 8 steps by display mode register 1 (dspm1). (4) hardware for key scan application ? generates an interrupt signal (intks) indicating key scan timing ? timing in which key scan data is output can be detected by key scan flag (ksf). ? whether key scan timing is inserted or not can be selected. (5) high-voltage output buffer that can directly drive fip (6) fip0 through fip15 pins are connected to pull-down resistors. fip16 through fip47 pins can be connected to pull-down resistors by mask option (mask rom model only). the m PD78F0228 does not have pull-down resistors). of the 48 fip output pins of the m pd780228 subseries, fip16 through fip47 are multiplexed with port pins. fip0 through fip15 are dedicated output pins. fip16 through fip47 can be used as port pins when fip display is disabled by bit 7 (dspen) of the display mode register 0 (dspm0). even when fip display is enabled, the fip output pins not used for display signal output can be used as port pins. table 11-1. fip output pins and multiplexed port pins fip pin name multiplexed port name i/o fip16-fip23 p70-p77 i/o port fip24-fip31 p80-p87 i/o port fip32-fip39 p90-p97 i/o port fip40-fip47 p100-p107 output port
chapter 11 fip controller/driver 128 11.2 configuration of fip controller/driver the fip controller/driver consists of the following hardware. table 11-2. fip controller/driver configuration item configuration display 48 control register display mode register 0 (dspm0) display mode register 1 (dspm1) display mode register 2 (dspm2) figure 11-1. fip controller/driver block diagram internal bus display data memory display data selector port output latch high-voltage buffer fip0 fip16/p70 fip47/p107 display data latch
chapter 11 fip controller/driver 129 11.3 registers controlling fip controller/driver 11.3.1 control registers the following three types of registers control the fip controller/driver. ? display mode register 0 (dspm0) ? display mode register 1 (dspm1) ? display mode register 2 (dspm2) (1) display mode register 0 (dspm0) dspm0 performs the following setting. ? enables or disables display ? number of fip output pins dspm0 is set by using a 1-bit or 8-bit memory manipulation instruction. the value of this register is set to 10h by reset input.
chapter 11 fip controller/driver 130 figure 11-2. display mode register 0 format dspen enables or disables fip 0 disables 1 enables fout5 fout4 fout3 fout2 fout1 fout0 number of fip output pins 0 1 0 1 1 1 17-24 0 1 1 1 1 1 25-32 1 0 0 1 1 1 33-40 1 0 1 1 1 1 41-48 others setting prohibited cautions 1. be sure to set bit 6 to 0. 2. do not write data to the bits other than dspen when bit 7 (dspen) = 1. 3. be sure to set the output latch of the multiplexed port of a pin used for fip output to 0. < 7 > dspen 6 0 5 fout5 4 fout4 3 fout3 2 fout2 1 fout1 0 fout0 symbol dspm0 address ff90h at reset 10h r/w r/w
chapter 11 fip controller/driver 131 (2) display mode register 1 (dspm1) dspm1 performs the following setting: ? blanking width of fip output signal ? number of display patterns dspm1 is set by using an 8-bit memory manipulation instruction. the value of this register is set to 01h by reset input. figure 11-3. display mode register 1 format fblk2 fblk1 fblk0 blanking width of fip output signal 0 0 0 1/16 0 0 1 2/16 0 1 0 4/16 0 1 1 6/16 1 0 0 8/16 1 0 1 10/16 1 1 0 12/16 1 1 1 14/16 fpat4 fpat3 fpat2 fpat1 fpat0 number of display patterns 000012 000103 000114 001005 001016 001107 001118 010009 0100110 0101011 0101112 0110013 0110114 0111015 0111116 others setting prohibited caution do not write data to the display mode register 1 (dspm1) when bit 7 (dspen) of the display mode register 0 (dspm0) is 1. 7 fblk2 6 fblk1 5 fblk0 4 fpat4 3 fpat3 2 fpat2 1 fpat1 0 fpat0 symbol dspm1 address ff91h at reset 01h r/w r/w
chapter 11 fip controller/driver 132 (3) display mode register 2 (dspm2) dspm2 performs the following setting. it also indicates the status of the display timing/key scan. ? insertion of key scan timing ? display cycle (tdsp) dspm2 is set by using a 1-bit or 8-bit memory manipulation instruction. however, only bit 7 (ksf) can be read by a 1-bit memory manipulation instruction. the value of this register is initialized to 00h by reset input. figure 11-4. display mode register format ksf status of key scan cycle 0 other than key scan cycle 1 key scan cycle ksm selects insertion of key scan cycle 0 not inserted 1 inserted fcyc1 fcyc0 display cycle 002 12 /f x (819.2 m s) 012 11 /f x (409.6 m s) 102 10 /f x (204.8 m s) 1 1 setting prohibited cautions 1. be sure to set bits 2 through 5 to 0. 2. do not write data to the display mode register 2 (dspm2) when bit 7 (dspen) of the display mode register 0 (dspm0) is 1. remarks 1. f x : main system clock oscillation frequency 2. ( ): f x = 5.0 mhz < 7 > ksf 6 ksm 5 0 4 0 3 0 2 0 1 fcyc1 0 fcyc0 symbol dspm2 address ff92h at reset 00h r/w r/w
chapter 11 fip controller/driver 133 11.3.2 one display period and blanking width the fip output signals are blanked equally at the beginning and end of the display period by the blanking width set by bits 0 through 2 (fblk0 through fblk2) of the display mode register 1 (dspm1). figure 11-5. blanking width of fip output signal 1 display period = t dsp 1/16 1/8 1/4 1/16 1/8 1/4 fip output signal (blanking width: 1/16) fip output signal (blanking width: 2/16) fip output signal (blanking width: 4/16)
chapter 11 fip controller/driver 134 11.4 display data memory the display data memory is a 96-byte ram area that stores data to be displayed, and is mapped to addresses fa00h through fa5fh. the fip controller reads the data stored in the display data memory independently of the cpu operation for fip display (dma operation). the area of the display data memory not used for display can be used as a normal ram area. at key scan timing, all the fip output pins are cleared to 0, and the data of the output latches of ports 7 through 10 are output to fip16/p70 through fip47/p107. the address location of the display data memory is as follows: ? with 48 fip output pins and 16 patterns the addresses of the display data memory corresponding to the data output at each display timing (t0 through t15) are as shown in figure 11-6 (for example, t0 = fa00h through fa05h, and t1 = fa06h through fa0bh). when 48 fip output pins (fip0 through fip47) are used, one block of display data consists of 6 bytes. fip output pins 0 (fip0) through 47 (fip47) correspond to one block of display data sequentially, starting from the least significant bit toward the most significant bit. figure 11-6. relation between address location of display data memory and fip output (with 48 fip output pins and 16 patterns) t3 t2 t1 t0 47 40 (fip output pins) address display timing fa5ah-fa5fh 7 0 5 fh 5eh 5dh 5ch 5bh 5ah t15 59h 58h 57h 56h 55h 54h t14 17h 16h 15h 14h 13h 12h 11h 10h 0fh 0eh 0dh 0ch 0bh 0ah 09h 08h 07h 06h 05h 04h 03h 02h 01h 00h t ks fa54h-fa59h fa12h-fa17h fa0ch-fa11h fa06h-fa0bh fa00h-fa05h
chapter 11 fip controller/driver 135 11.5 key scan flag and key scan data 11.5.1 key scan flag the key scan flag (ksf) is set to 1 during key scan timing, and is automatically reset to 0 at display timing. ksf is mapped to bit 7 of the display mode register 2 (dspm2) and can be tested in 1-bit units. it cannot be written, however. by testing ksf, it can be determined whether key scan timing is in progress, and whether key input data is correct can be checked. whether key scan timing is inserted or not can be selected by using the key scan timing insertion specification flag (ksm) (bit 6 of the display mode register 2 (dspm2)). 11.5.2 key scan data data stored to ports 7 through 10 are output from the fip16 through fip47 pins during key scan timing. caution if scanning is performed in such a manner that both a segment and a digit turn on during key scan timing, the display may flicker.
chapter 11 fip controller/driver 136 11.6 leakage emission of fluorescent indicator panel leakage emission may take place when a fluorescent indicator panel is driven by the m pd780228 subseries. the possible causes of this leakage emission are as follows: (1) short blanking time figure 11-7 shows the signal waveforms of a 2-digit display where the first digit t0 lights and the second digit remains dark. if the blanking time is too short as shown in this figure, the t1 signal rises before the segment signal is deasserted, causing leakage emission. generally, the blanking time must be about 20 m s. determine the set value of the display mode register 1 (dspm1), taking this into consideration. figure 11-7. leakage emission because of short blanking time blanking width leakage emission occurs t0 t1 s0
chapter 11 fip controller/driver 137 (2) segment-grid capacitance of fluorescent indicator panel even if a sufficiently long blanking time is ensured as shown in figure 11-9, leakage emission may still occur. this is because the fluorescent indicator panel has a capacitance between the grid and segment, as indicated by c sg in the figure, and the timing signal pin is raised via c sg . if the voltage of the timing signal rises beyond the cutoff voltage (e k ) as shown in figure 11-9, leakage emission occurs. this whisker-like voltage changes with the values of c sg and internal pull-down resistor (r l ). the greater the value of c sg , and the greater the value of r l , the higher this voltage, increasing the possibility of the occurrence of leakage emission. the value of c sg differs depending on the display area of the fluorescent indicator panel. the larger the area, the higher the c sg . therefore, the value of the pull-down resistor differs depending on the size of the fluorescent indicator panel, in order to prevent leakage emission. because the value of the pull-down resistor that can be connected by mask option is relatively high, the leakage emission may not be suppressed by the internal pull-down resistor alone. in case sufficient display quality cannot be obtained, deepen the back bias (increase e k ), attach a filter to the fluorescent indicator panel, or connect an external pull-down resistor of several 10 k w to the timing signal pin. the likelihood of leakage emission caused by c sg occuring changes depending on the duty cycle of the whisker voltage vis-a-vis the total display cycle. the fewer the number of display digits, the less likelihood of occurrence of leakage emission. lowering the display luminance also has an effect of suppressing the leakage emission. figure 11-8. leakage emission caused by c sg segment grid filament fip v dd e k c sg v load r l r l s0 t0 ?0 v +5 v e k : cutoff voltage r l : internal pull-down resistor pd780228 m
chapter 11 fip controller/driver 138 figure 11-9. leakage emission caused by c sg t0 t1 s0 e k
chapter 11 fip controller/driver 139 11.7 calculation of total power dissipation the following three power dissipation are available for the m pd780208 subseries. the sum of the three power dissipation should be less than the total power dissipation p t (refer to figure 11-10 ) (80 % or less of ratings is recommended). <1> cpu power dissipation: calculate v dd (max.) i dd (max.). <2> output pin power dissipation: power dissipation when maximum current flows into each fip output pin. <3> pull-down resistor power dissipation: power dissipation by pull-down resistor incorporated in fip output pin. figure 11-10. total power dissipation p t (t a = C40 to +85 c) the following is how to calculate total power dissipation for the example in figure 11-11. example assume the following conditions: v dd = 5.5 v, 5.0 mhz oscillation supply current (i dd ) = 21.0 ma fip output: 11 grids 10 segments (blanking width = 1/16: when fblk0-fblk2 = 000b) maximum current at the grid pin is 10 ma. maximum current at the segment pin is 3 ma. at the key scan timing, fip output pin is off. fip output voltage: grid v od = v dd C 2 v (voltage drop of 2 v) segments v od = v dd C 0.5 v (voltage drop of 0.5 v) fluorescant display control voltage (v load ) = C35 v mask option pull-down resistor = 25 k w 800 600 400 200 total power dissipation p t [mw] ?0 0 +40 +80 temperature [?]
chapter 11 fip controller/driver 140 by placing the above conditions in calculation <1> to <3>, the total dissipation can be worked out. <1> cpu power dissipation: 5.5 v 21.0 ma = 115.5 mw <2> output pin power dissipation: grid (v dd C v od ) total current value of each grid (1 C blanking width) = the no. of grids + 1 2 v 10 ma 11 grids (1 C 1 ) = 17.2 mw 11 grids + 1 16 segment (v dd C v od ) total segment current value of illuminated dots (1 C blanking width) = the no. of grids + 1 0.5 v 3 ma 31 dots (1 C 1 ) = 3.6 mw 11 grids + 1 16 <3> pull-down resistor power dissipation: grid (v dd C v load ) 2 the no. of grids (1 C blanking width) = pull-down resistor value the no. grids + 1 (5.5 v C 2 v C (C35 v)) 2 11 grids (1 C 1 ) = 50.9 mw 25 k w 11 grids + 1 16 segment (v od C v load ) 2 the no. of illuminated dots (1 C blanking width)= pull-down resistor value the no. of grids + 1 (5.5 v C 0.5 v C (C35 v)) 2 31 dots (1 C 1 ) = 155.0 mw 25 k w 11 grids + 1 16 total power dissipation = <1> + <2> + <3> = 115.5 + 17.2 + 3.6 + 50.9 + 155.0 = 342.2 mw in this example, the total power dissipation do not exceed the rating of the total power dissipation, so there is no problem in power dissipation. however, when the total power dissipation exceeds the rating of the total power dissipation, it is necessary to lower the power dissipation. to reduce power dissipation, reduce the number of pull-down resistor.
chapter 11 fip controller/driver 141 figure 11-11. relationship between display data memory and fip output with 10 segments-11 digits displayed 012 34 567 8910 i j i am pm sun mon tue wed thu fri sat j j a g d b c f e j ihgfedcba 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (fip output pins : fip0-fip20) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 h display data memory f f f f f f f f f f f a a a a a a a a a a a 2 1 1 1 1 1 0 0 0 0 0 0 d a 7 4 1 e b 8 5 2 h h h h h h h h h h h , , , , , , , , , , , f f f f f f f f f f f a a a a a a a a a a a 1 1 1 1 1 1 0 0 0 0 0 f c 9 6 3 0 d a 7 4 1 h h h h h h h h h h h , , , , , , , , , , , f f f f f f f f f f f a a a a a a a a a a a 1 1 1 1 1 0 0 0 0 0 0 e b 8 5 2 f c 9 6 3 0 h h h h h h h h h h h , , , , , , , , , , ,
chapter 11 fip controller/driver 142 [memo]
chapter 12 interrupt functions 143 chapter 12 interrupt functions 12.1 interrupt function types the following three types of interrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally even in a disabled state. it does not undergo interrupt priority control and is given top priority over all other interrupt requests. it generates a standby release signal. one interrupt request source from the watchdog timer is incorporated as a non-maskable interrupt. (2) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register (pr0l and pr0h). multiple high priority interrupts can be applied to low priority interrupts. if two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority (see table 12-1 ). a standby release signal is generated. four external interrupt request sources and six internal interrupt request sources are incorporated as maskable interrupts. (3) software interrupt this is a vectored interrupt to be generated by executing the brk instruction. it is acknowledged even in a disabled state. the software interrupt does not undergo interrupt priority control.
chapter 12 interrupt functions 144 12.2 interrupt sources and configuration a total of 12 non-maskable, maskable and software interrupts are incorporated in the interrupt sources (see table 12-1 ). table 12-1. interrupt sources interrupt default interrupt source internal/ type priority note 1 name trigger external non- intwdt overflow of watchdog timer internal 0004h (a) maskable (with watchdog timer mode 1 selected) maskable 0 intwdt overflow of watchdog timer (b) (with internal timer mode selected) 1 intp0 detection of pin input edge external 0006h (c) 2 intp1 0008h 3 inttm10 detection of timer input edge 000ah (d) 4 inttm11 000ch 5 intks key scan timing from fip controller/driver internal 000eh (b) 6 intcsi3 end of transfer of serial interface 0010h 7 inttm50 coincidence of 8-bit timer (tm50) 0012h 8 inttm51 coincidence of 8-bit timer (tm51) 0014h 9 intad end of a/d conversion 0016h software brk execution of brk instruction 003eh (e) notes 1. if two or more maskable interrupt requests are simultaneously generated, they are controlled according to the default priority. 0 indicates the highest priority and 9 indicates the lowest. 2. (a) through (e) under the heading basic configuration type correspond to (a) through (e) in figure 12-1. basic configuration type note 2 vector table address
chapter 12 interrupt functions 145 figure 12-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (c) external maskable interrupt (intp0) (b) internal maskable interrupt internal bus vector table address generator priority control circuit interrupt request standby release signal internal bus mk ie pr isp vector table address generator priority control circuit standby release signal if interrupt request external interrupt rise/fall edge enable register (egp, egn) edge detector internal bus mk ie pr isp vector table address generator priority control circuit standby release signal if interrupt request
chapter 12 interrupt functions 146 figure 12-1. basic configuration of interrupt function (2/2) (d) external maskable interrupt (inttm10, inttm11) (e) software interrupt if : interrupt request flag ie : interrupt enabled flag isp: in-service priority flag mk : interrupt mask flag pr : priority specify flag internal bus vector table address generator priority control circuit interrupt request internal bus mk ie pr isp vector table address generator priority control circuit standby release signal if interrupt request edge detector
chapter 12 interrupt functions 147 12.3 interrupt function control registers the following six types of registers are used to control the interrupt functions. ? interrupt request flag register (if0l and if0h) ? interrupt mask flag register (mk0l and mk0h) ? priority specify flag register (pr0l and pr0h) ? external interrupt rising edge enable register (egp) ? external interrupt falling edge enable register (egn) ? program status word (psw) table 12-2 gives a listing of interrupt request flags, interrupt mask flags and priority specify flag names corresponding to interrupt request sources. table 12-2. various flags corresponding to interrupt request sources interrupt request source interrupt request flag interrupt mask flag priority specify flag register register register intwdt wdtif note if0l wdtmk note mk0l wdtpr note pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 inttm10 tmif10 tmmk10 tmpr10 inttm11 tmif11 tmmk11 tmpr11 intks ksif ksmk kspr intcsi3 csiif3 csimk3 csipr3 inttm50 tmif50 tmmk50 tmpr50 inttm51 tmif51 if0h tmmk51 mk0h tmpr51 pr0h intad adif admk adpr note the wdtif, wdtmk, and wdtpr flags are interrupt control flags used when the watchdog timer is used as an interval timer.
chapter 12 interrupt functions 148 (1) interrupt request flag registers (if0l and if0h) the interrupt request flag is set to (1) when the corresponding interrupt request is generated or an instruction is executed. it is cleared to (0) when an instruction is executed upon acknowledgment of an interrupt request or upon application of reset input. if0l and if0h are set with a 1-bit or 8-bit memory manipulation instruction. when if0l and if0h are used in combination as a 16-bit register if0, they are set with a 16-bit memory operation instruction. reset input sets these registers to 00h. figure 12-2. interrupt request flag register format cautions 1. wdtif flag is r/w enabled only when a watchdog timer is used as an interval timer. if a watchdog timer is used in watchdog timer mode 1, set wdtif flag to 0. 2. be sure to set bits 2 through 7 of if0h to 0. tmif51 if0h 765432 <1> <0> xxif interrupt request flag ffe1h adif 0 0 0 0 0 0 00h r/w 0 no interrupt request signal 1 interrupt request signal is generated: interrupt request state wdtif if0l <7> <6> <5> <4> <3> <2> symbol <1> <0> ffe0h pif0 tmif10 pif1 tmif11 ksif csiif3 tmif50 address at reset r/w 00h r/w
chapter 12 interrupt functions 149 (2) interrupt mask flag registers (mk0l and mk0h) the interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. mk0l and mk0h are set with a 1-bit or 8-bit memory manipulation instruction. when mk0l and mk0h are used in combination as a 16-bit register mk0, they are set with a 16-bit memory operation instruction. reset input sets these registers to ffh. figure 12-3. interrupt mask flag register format cautions 1. if wdtmk flag is read when a watchdog timer is used in watchdog timer mode 1, mk0 value becomes undefined. 2. because port 0 has a dual function as the external interrupt request input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, 1 should be set in the interrupt mask flag before using the output mode. 3. be sure to set bits 2 through 7 of mk0h to 1. tmmk51 mk0h 765432 <1> <0> xxmk interrupt serving and standby mode control ffe5h admk 1 1 1 1 1 1 ffh r/w 0 interrupt serving enabled, standby mode release enabled 1 interrupt serving disabled, standby mode release disabled wdtmk mk0l <7> <6> <5> <4> <3> <2> symbol <1> <0> ffe4h pmk0 tmmk10 pmk1 tmmk11 ksmk csimk3 tmmk50 address at reset r/w ffh r/w
chapter 12 interrupt functions 150 (3) priority specify flag registers (pr0l and pr0h) the priority specify flag is used to set the corresponding maskable interrupt priority orders. pr0l and pr0h are set with a 1-bit or 8-bit memory manipulation instruction. when pr0l and pr0h are used in combination as a 16-bit register pr0, they are set with a 16-bit memory operation instruction. reset input sets these registers to ffh. figure 12-4. priority specify flag register format tmpr51 pr0h 765432 <1> <0> xxpr priority level selection ffe9h adpr 1 1 1 1 1 1 ffh r/w 0 high priority level 1 low priority level wdtpr pr0l <7> <6> <5> <4> <3> <2> symbol <1> <0> ffe8h ppr0 tmpr10 ppr1 tmpr11 kspr csipr3 tmpr50 address at reset r/w ffh r/w cautions 1. when a watchdog timer is used in watchdog timer mode 1, set 1 in wdtpr flag. 2. be sure to set bits 2 through 7 of pr0h to 1.
chapter 12 interrupt functions 151 (4) external interrupt rising edge enable register (egp) this register specifies whether the valid edges of intp0 and intp1 are specified to be the rising edge. it is set by using a 1-bit or 8-bit memory manipulation instruction. the value of this register is initialized to 00h by reset input. figure 12-5. external interrupt rising edge enable register format 0 0 0 0 0 0 egp1 egp0 egp 765 0 disable 1 enable egpn enables or disables specification of rising edge of intpn as valid edge (n = 0 or 1) address at reset r/w 43210 ff48h 00h r/w (5) external interrupt falling edge enable register (egn) this register specifies whether the valid edges of intp0 and intp1 are specified to be the falling edge. it is set by using a 1-bit or 8-bit memory manipulation instruction. the value of this register is initialized to 00h by reset input. figure 12-6. external interrupt falling edge enable register format 0 0 0 0 0 0 egn1 egn0 egn 765 0 disable 1 enable egnn enables or disables specification of falling edge of intpn as valid edge (n = 0 or 1) address at reset r/w 43210 ff49h 00h r/w
chapter 12 interrupt functions 152 (6) program status word (psw) the program status word is a register to hold the instruction execution result and the current status for interrupt request. the ie flag to set maskable interrupt enable/disable and the isp flag to control multiple interrupt processing are mapped. besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (ei and di). when a vectored interrupt request is acknowledged and the brk instruction is executed, the contents of the psw is automatically saved into a stack and the ie flag is reset to (0). if a maskable interrupt request is acknowledged, the contents of the priority specify flag of the acknowledged interrupt are transferred to the isp flag. the contents of the psw is also saved into the stack with the push psw instruction. it is reset from the stack with the reti, retb, and pop psw instructions. reset input sets psw to 02h. figure 12-7. program status word configuration 0 6543210 7 psw ie z rbs1 ac rbs0 0 isp cy 02h at reset ie 0 1 interrupt request acknowledge enable/disable disable enable isp 1 priority of interrupt currently being received high-priority interrupt servicing (low-priority interrupt disable) interrupt request not acknowledged or low-priority interrupt servicing (all-maskable interrupts enable) used when normal instruction is executed symbol
chapter 12 interrupt functions 153 12.4 interrupt servicing operations 12.4.1 non-maskable interrupt request acknowledge operation a non-maskable interrupt request is unconditionally acknowledged even if in an interrupt acknowledge disable state. it does not undergo interrupt priority control and has highest priority over all other interrupts. if a non-maskable interrupt request is acknowledged, the contents are saved in the stacks, psw and pc, in that order, the ie and isp flags are reset to 0, and the vector table contents are loaded into pc and branched. a new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following reti instruction execution) and one main routine instruction is executed. if a new non-maskable interrupt request is generated twice or more during non-maskable interrupt service program execution, only one non-maskable interrupt request is acknowledged after termination of the non-maskable interrupt service program execution. figure 12-8 shows the flowchart illustrating how the non-maskable interrupt request occurs and is acknowledged. figure 12-9 shows the acknowledge timing of the non-maskable interrupt. figure 12-10 shows acknowledge operation of multiple non-maskable interrupts.
chapter 12 interrupt functions 154 figure 12-8. flowchart of occurrence and acknowledge non-maskable interrupt start wdtm4 = 1 (with watchdog timer mode selected) ? interval timer no overflow in wdt ? no yes wdtm3 = 0 (with non-maskable interrupt selected) ? reset processing no yes yes interrupt request generation wdt interrupt servicing ? interrupt request reserve no yes interrupt control register unaccessed ? yes no yes interrupt service start wdtm : watchdog timer mode register wdt : watchdog timer figure 12-9. non-maskable interrupt request acknowledge timing wdtif : watchdog timer interrupt request flag instruction instruction psw and pc save, jump to interrupt servicing interrupt servicing program cpu processing wdtif an interrupt request generated during this period is acknowledged at the timing indicated by .
chapter 12 interrupt functions 155 figure 12-10. non-maskable interrupt request acknowledge operation (a) if a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution (b) if two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution main routine nmi request <1> 1 instruction execution nmi request <2> nmi request <1> execution nmi request <2> reserve reserved nmi request <2> processing main routine nmi request <1> 1 instruction execution nmi request <2> nmi request <1> execution nmi request <2> reserve nmi request <3> reserve reserved nmi request <2> processing nmi request <3> nmi request <3> is not acknowledged (nmi request is acknowledged only once even if it occurs two times or more).
chapter 12 interrupt functions 156 12.4.2 maskable interrupt request acknowledge operation a maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask (mk) flag is cleared to 0. a vectored interrupt request is acknowledged in an interrupt enable state (with ie flag set to 1). however, a low-priority interrupt request is not acknowledged during high-priority interrupt service (with isp flag reset to 0). wait times from maskable interrupt request generation to interrupt servicing are shown in table 12-3. for the timing to acknowledge an interrupt request, refer to figures 12-12 and 12-13. table 12-3. times from maskable interrupt request generation to interrupt service minimum time maximum time note when xxpr = 0 7 clocks 32 clocks when xxpr = 1 8 clocks 33 clocks note if an interrupt request is generated just before a divide instruction, the wait time is maximized. remark 1 clock : 1 (f cpu : cpu clock) f cpu if two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority with the priority specify flag is acknowledged first. if two or more requests are assigned the same priority by the interrupt priority specify flag, the one with the higher default priority is acknowledged first. any reserved interrupt requests are acknowledged when they become acknowledgeable. figure 12-11 shows interrupt request acknowledge algorithms. if a maskable interrupt request is acknowledged, the contents are saved in the stacks, in the order of program status word (psw), program counter (pc), the ie flag is reset to 0, and the acknowledged interrupt request priority specify flag contents are transferred to the isp flag. further, the vector table data determined for each interrupt request is loaded into pc and branched. restore from the interrupt is possible with the reti instruction.
chapter 12 interrupt functions 157 figure 12-11. interrupt request acknowledge processing algorithm start xxif = 1? no yes (interrupt request generation) xxmk = 0? yes no interrupt request reserve xxpr = 0? no (low priority) yes (high priority) any simultaneously generated xxpr = 0 interrupt requests ? interrupt request reserve yes no any simultaneously generated high-priority interrupt requests ? interrupt request reserve yes no ie = 1? interrupt request reserve no yes isp = 1? interrupt request reserve no vectored interrupt servicing any high- priority interrupt request among simultaneously generated xxpr = 0 interrupts ? interrupt request reserve yes no ie = 1? yes interrupt request reserve no vectored interrupt servicing yes xxif : interrupt request flag xxmk : interrupt mask flag xxpr : priority specify flag ie : flag that controls maskable interrupt request acknowledge (1 = enable, 0 = disable) isp : flag indicating priority of interrupt currently processed (0 = interrupt with high priority is processed. 1 = interrupt request is not acknowledged or interrupt with low priority processed).
chapter 12 interrupt functions 158 figure 12-12. interrupt request acknowledge timing (minimum time) remark 1 clock : 1 (f cpu : cpu clock) f cpu figure 12-13. interrupt request acknowledge timing (maximum time) remark 1 clock : 1 (f cpu : cpu clock) f cpu 12.4.3 software interrupt request acknowledge operation a software interrupt request is acknowledged by brk instruction execution. software interrupt cannot be disabled. if a software interrupt request is acknowledged, it is saved in the stacks, program status word (psw), program counter (pc), in that order, the ie flag is reset to 0 and the contents of the vector tables (003eh and 003fh) are loaded into pc and branched. return from the software interrupt is possible with the retb instruction. caution do not use the reti instruction for returning from the software interrupt. instruction instruction psw and pc save, jump to interrupt servicing interrupt servicing program cpu processing xxif (xxpr = 1) 8 clocks xxif (xxpr = 0) 7 clocks 6 clocks instruction divide instruction psw and pc save, jump to interrupt servicing interrupt servicing program cpu processing xxif (xxpr = 1) 33 clocks xxif (xxpr = 0) 32 clocks 6 clocks 25 clocks
chapter 12 interrupt functions 159 12.4.4 multiple interrupt servicing acknowledging another interrupt while one interrupt is processed is called multiple interrupts. a multiple interrupt is not generated unless acknowledge of the interrupt request is enabled (ie = 1) (except the non-maskable interrupt). when an interrupt request is acknowledged, the other interrupt requests are disabled (ie = 0). to enable a multiple interrupt, therefore, the ie flag must be set to 1 by executing the ei instruction during interrupt servicing and the interrupt must be enabled. even in the ei status, a multiple interrupt may not be enabled. in such a case, it is controlled according to the priority of the interrupt. an interrupt has two types of priorities: default priority and programmable priority. the multiple interrupt is controlled by the programmable priority. in the ei status, if an interrupt request having the same as or higher priority than that of the interrupt currently processed is generated, and it is acknowledged as the multiple interrupt. if an interrupt request with a priority lower than that of the interrupt currently processed is generated, the multiple interrupt is not acknowledged. if an interrupt is disabled, or if a multiple interrupt is not acknowledged because it has a low priority, the interrupt is kept pending. after the processing of the current interrupt has been completed, and after one instruction of the main processing has been executed, the pending interrupt is acknowledged. multiple interrupts are not acknowledged while the non-maskable interrupt is processed. table 12-4 shows interrupt requests enabled for multiple interrupts. figure 12-14 shows multiple interrupt examples. table 12-4. interrupt request enabled for multiple interrupt during interrupt servicing multiple interrupt request non-maskable maskable interrupt request interrupt request xx pr = 0 xx pr = 1 interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 non-maskable interrupt maskable interrupt isp = 0 isp = 1 software interrupt remarks 1. : multiple interrupt enable : multiple interrupt disable 2. isp and ie are flags included in psw. isp = 0 : high-priority interrupt servicing isp = 1 : interrupt request is not acknowledged or low-priority interrupt servicing ie = 0 : interrupt request acknowledge disabled ie = 1 : interrupt request acknowledge enabled 3. xxpr is a flag included in pr0l and pr0h. xxpr = 0 : high-priority flag xxpr = 1 : low-priority flag
chapter 12 interrupt functions 160 figure 12-14. multiple interrupt examples example 1. two multiple interrupts are generated. two interrupt requests intyy and intzz are acknowledged and multiple interrupts are generated while interrupt intxx request is processed. before each interrupt request is acknowledged, the ei instruction is always issued and the interrupt request is enabled. example 2. multiple interrupt is not generated because of its priority. intyy that occurs while intxx is processed is not acknowledged and a multiple interrupt is not generated, because the priority of intyy is lower than that of intxx. intyy is reserved and is acknowledged after one instruction of the main processing has been executed. pr = 0 : high-priority interrupt pr = 1 : low-priority interrupt ie = 0 : interrupt acknowledge disabled ei main processing intxx (pr = 0) ei intxx servicing intyy (pr = 1) ie = 0 reti 1 instruction execution ie = 0 reti intyy servicing ei main processing intxx (pr = 1) ei intxx servicing intyy (pr = 0) reti ie = 0 ei intyy servicing intzz (pr = 0) reti ie = 0 intzz servicing reti ie = 0
chapter 12 interrupt functions 161 example 3. multiple interrupt is not generated because an interrupt is not processed. because interrupts are not enabled (the ei instruction is not issued) in interrupt processing intxx, interrupt request intyy is not accepted, and therefore, the interrupt is not nested. intyy request is kept pending, and is accepted after main processing 1 instruction has been executed. pr = 0 : high priority level ie = 0 : disables accepting interrupt request ei main processing intxx (pr = 0) intxx servicing intyy (pr = 0) ie = 0 reti 1 instruction execution ie = 0 reti intyy servicing
chapter 12 interrupt functions 162 12.4.5 interrupt request reserve some instructions keep the acceptance of an interrupt request, if one occurs, pending until execution of the next instruction is completed. these instructions (that keep interrupt requests pending) are listed below. ? mov psw, #byte ? mov a, psw ? mov psw, a ? mov1 psw.bit, cy ? mov1 cy, psw.bit ? and1 cy, psw.bit ? or1 cy, psw.bit ? xor1 cy, psw.bit ? set1 psw.bit ? clr1 psw.bit ? retb ? reti ? push psw ? pop psw ? bt psw.bit, $addr16 ? bf psw.bit, $addr16 ? btclr psw.bit, $addr16 ?ei ?di ? manipulation instructions for if0l, if0h, mk0l, mk0h, pr0l, pr0h, and intm0 registers caution the brk instruction is not included in the above list of instructions. the software interrupt that is started by execution of the brk instruction, however, clears the ie flag to 0. therefore, even if a maskable interrupt request is generated while the brk instruction is being executed, the interrupt request is not accepted. however, a non-maskable interrupt request is accepted. figure 12-15 shows the timing at which an interrupt request is reserved. figure 12-15. interrupt request reserve remarks 1. instruction n : interrupt request reserve instruction 2. instruction m : instruction except interrupt request reserve instructions 3. operation of xxif (interrupt request) is not effected by xxpr (priority level) value. instruction m psw and pc save, jump to interrupt servicing interrupt servicing program cpu processing xxif instruction n
chapter 13 standby function 163 chapter 13 standby function 13.1 standby function and configuration 13.1.1 standby function the standby function is intended to decrease the power consumption of the system. the following two modes are available. (1) halt mode halt instruction execution sets the halt mode. the halt mode is intended to stop the cpu operation clock. the system clock oscillator continues oscillating. in this mode, the current consumption cannot be decreased as in the stop mode. the halt mode is valid to restart immediately upon interrupt request and to carry out intermittent operations like clock operations. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the main system clock oscillator stops and the whole system stops. the cpu current consumption can be considerably decreased. data memory low-voltage hold (down to v dd = 2 v) is possible. thus, the stop mode is effective to hold data memory contents with ultra-low current consumption. because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out. however, because a wait time is necessary to secure the oscillation stabilization time after the stop mode is cleared, select the halt mode if it is necessary to start processing immediately upon interrupt request. in any mode, all the contents of the register, flag and data memory just before standby mode setting are held. the input/output port output latch and output buffer statuses are also held. cautions 1. when proceeding to the stop mode, be sure to stop the peripheral hardware operation and execute the stop instruction. 2. in order to decrease the power consumption in the a/d converter, clear bit 7 (cs0) in the a/ d converter mode register (adm0) to 0 and stop a/d conversion operation before executing a halt or stop instruction.
chapter 13 standby function 164 13.1.2 standby function control register the wait time after the stop mode is cleared upon interrupt request until the oscillation stabilizes is controlled with the oscillation stabilization time select register (osts). osts is set with a 1-bit/8-bit memory manipulation instruction. reset input sets osts to 04h. therefore, when the stop mode is cleared with reset input, the time until it is cleared is 2 16 /fx. figure 13-1. oscillation stabilization time select register format caution the wait time after stop mode clear does not include the time (see a below) from stop mode clear to clock oscillation start, regardless of clearance by reset input or by interrupt request generation. remarks 1. f x : main system clock frequency 2. values in parentheses apply to operation with f x = 5.0 mhz v ss stop mode clear x1 pin voltage waveform a 6543210 7 symbol osts 0 0 0 0 0 osts2 osts1 osts0 fffah 04h r/w address at reset r/w osts2 0 0 0 osts1 0 0 1 01 10 others selection of oscillation stabilization time at stop mode clear 2 11 /f x (410 s) 2 13 /f x (1.64 ms) 2 14 /f x (3.28 ms) osts0 0 1 0 2 15 /f x (6.55 ms) 1 2 16 /f x (13.1 ms) setting prohibited 0 m
chapter 13 standby function 165 13.2 standby function operations 13.2.1 halt mode (1) halt mode set and operating status the halt mode is set by executing the halt instruction. the operating status in the halt mode is described below. table 13-1. halt mode operating status item operating status clock generator oscillation enabled. clock supply to the cpu stops. cpu operation stop. port (output latch) status before halt instruction execution is held. 8-bit remote control timer operation enabled. 8-bit pwm timer watchdog timer a/d converter serial interface fip controller/driver operation disabled. external interrupt request operation enabled.
chapter 13 standby function 166 (2) halt mode clear the halt mode can be cleared with the following three types of sources. (a) clear upon unmasked interrupt request an unmasked interrupt request is used to clear the halt mode. if interrupt request acknowledge is enabled, vectored interrupt service is carried out. if disabled, the next address instruction is executed. figure 13-2. halt mode clear upon interrupt request generation remarks 1. the broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged. 2. wait time will be as follows: ? when vectored interrupt service is carried out : 8 to 9 clocks ? when vectored interrupt service is not carried out : 2 to 3 clocks (b) clear upon non-maskable interrupt request the halt mode is cleared and vectored interrupt service is carried out whether interrupt request acknowledge is enabled or disabled. halt instruction standby release signal wait wait halt mode operating mode operating mode clock oscillation
chapter 13 standby function 167 (c) clear upon reset input as is the case with normal reset operation, a program is executed after branch to the reset vector address. figure 13-3. halt mode release by reset input remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 5.0 mhz. table 13-2. operation after halt mode release release source mkxx prxx ie isp operation maskable interrupt request 0 0 0 next address instruction execution 001 interrupt service execution 0 1 0 1 next address instruction execution 01 0 0 1 1 1 interrupt service execution 1 halt mode hold non-maskable interrupt request interrupt service execution reset input reset processing : dont care halt instruction reset signal wait (2 16 /f x : 13.1 ms) reset period halt mode operating mode oscillation stabilization wait status clock operating mode oscillation stop oscillation oscillation
chapter 13 standby function 168 13.2.2 stop mode (1) stop mode set and operating status the stop mode is set by executing the stop instruction. cautions 1. when the stop mode is set, x2 pin is internally pulled-up to v dd1 to suppress the leakage at the crystal oscillator. thus, do not use the stop mode in a system where an external clock is used for the main system clock. 2. because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction. after the wait set using the oscillation stabilization time select register (osts), the operating mode is set. the operating status in the stop mode is described below. table 13-3. stop mode operating status item operating status clock generator oscillation stop. cpu operation stop. output port (output latch) status before stop mode setting is held. 8-bit remote control timer operation stop. 8-bit pwm timer watchdog timer a/d converter serial interface operation enabled only when external input clock is selected as serial clock. fip controller/driver operation disabled. external interrupt request operation enabled.
chapter 13 standby function 169 (2) stop mode release the stop mode can be cleared with the following two types of sources. (a) release by unmasked interrupt request an unmasked interrupt request is used to release the stop mode. if interrupt request acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. if interrupt request acknowledge is disabled, the next address instruction is executed. figure 13-4. stop mode release by interrupt request generation remark the broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged. stop instruction standby release signal wait (time set by osts) stop mode operating mode oscillation stabilization wait status clock operating mode oscillation stop oscillation oscillation
chapter 13 standby function 170 (b) release by reset input the stop mode is cleared and after the lapse of oscillation stabilization time, reset operation is carried out. figure 13-5. release by stop mode reset input remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 5.0 mhz. table 13-4. operation after stop mode release release source mkxx prxx ie isp operation maskable interrupt request 0 0 0 next address instruction execution 001 interrupt service execution 0 1 0 1 next address instruction execution 01 0 0 1 1 1 interrupt service execution 1 stop mode hold reset input reset processing : dont care stop instruction reset signal wait (2 16 /f x : 13.1 ms) reset period stop mode operating mode oscillation stabilization wait status clock operating mode oscillation stop oscillation oscillation
chapter 14 reset function 171 chapter 14 reset function 14.1 reset function the following two operations are available to generate the reset signal. (1) external reset input with reset pin (2) internal reset by watchdog timer overrun time detection external reset and internal reset have no functional differences. in both cases, program execution starts at the address at 0000h and 0001h by reset input. when a low level is input to the reset pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status as shown in table 14-1. each pin has high impedance during reset input or during oscillation stabilization time just after reset clear. when a high level is input to the reset pin, the reset is cleared and program execution starts after the lapse of oscillation stabilization time (2 16 /f x ). the reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time (2 16 /f x ) (see figures 14-2 to 14- 4 ). cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. when the stop mode is cleared by reset, the stop mode contents are held during reset input. however, the port pin becomes high-impedance. figure 14-1. block diagram of reset function reset control circuit watchdog timer reset count clock stop overflow reset signal interrupt function
chapter 14 reset function 172 figure 14-2. timing of reset input by reset input figure 14-3. timing of reset due to watchdog timer overflow figure 14-4. timing of reset in stop mode by reset input reset internal reset signal port pin x1 delay delay normal operation oscillation stabilization time wait normal operation (reset processing) hi-z stop status (oscillation stop) reset period (oscillation stop) stop instruction execution watchdog timer overflow internal reset signal port pin x1 normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) hi-z reset internal reset signal port pin x1 delay delay normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) hi-z
chapter 14 reset function 173 table 14-1. hardware status after reset hardware status after reset program counter (pc) note 1 contents of reset vector table (0000h, 0001h) are set stack pointer (sp) undefined program status word (psw) 02h ram data memory undefined note 2 general-purpose register undefined note 2 port (output latch) ports 0-2, ports 4-10 (p0-p2, p4-p10) 00h port read (plr7-plr9) undefined port mode register (pm0, pm2, pm4-pm6) ffh pull-up resistor option register (pu0, pu2, pu4) 00h processor clock control register (pcc) 04h memory size select register (ims) cch note 3 internal expansion ram size select register (ixs) 0ch note 4 oscillation stabilization time select register (osts) 04h 8-bit remote control timer capture registers (cp10, cp11) 00h mode control register (tmc1) 00h 8-bit pwm timer timer registers (tm50, tm51) 00h compare registers (cr50, cr51) undefined mode control registers (tmc50, tmc51) 04h clock select registers (tcl50, tcl51) 00h watchdog timer clock select register (wdcs) 00h mode register (wdtm) 00h a/d converter conversion result register (adcrh0) undefined mode register (adm0) 00h analog input channel specification register (ads0) 00h serial interface shift register (sio3) undefined mode register (csim3) 00h fip controller/driver display mode register 0 (dspm0) 10h display mode register 1 (dspm1) 01h display mode register 2 (dspm2) 00h interrupt external interrupt rising edge enable register (egp) 00h external interrupt falling edge enable register (egn) 00h request flag registers (if0l, if0h) 00h mask flag registers (mk0l, mk0h) ffh priority specification flag registers (pr0l, pr0h) ffh notes 1. of the hardware units, only the contents of the pc are undefined during reset input or oscillation stabilization time wait. the statuses of the other hardware units are the same as those after reset. 2. the status after reset is retained in the standby mode. 3. be sure to set cfh when using the m pd780228. 4. after reset, be sure to set this bit to 0bh.
chapter 14 reset function 174 [memo]
175 chapter 15 m m m m m PD78F0228 chapter 15 m m m m m PD78F0228 the m PD78F0228 has a flash memory to which a program can be written or whose contents can be erased with the device mounted on the pc board of the target system. table 15-1 shows the differences between the flash memory model ( m PD78F0228) and mask rom models ( m pd780226 and 780228). table 15-1. differences between m m m m m PD78F0228 and mask rom models item m PD78F0228 mask rom models internal rom structure flash memory mask rom internal rom capacity 60k bytes m pd780226: 48k bytes m pd780228: 60k bytes changing internal rom capacity by memory possible note impossible size select register (ims) internal expansion ram size select register (ixs) provided not provided ic pin not provided provided v pp pin provided not provided mask option of connecting pull-up resistors not provided provided to p50 through p57 and p60 through p67 mask option of connecting pull-down resistors not provided provided to p70 through p77, p80 through p87, p90 through p97, and p100 through p107 note the flash memory capacity is set to 60k bytes by reset input. caution the flash memory model and mask rom model differ in terms of noise immunity. when replacing a flash memory model with a mask rom model in the course of experimental production to mass production, make a thorough evaluation with a cs model (not es model) of the mask rom model.
176 chapter 15 m m m m m PD78F0228 15.1 memory size select register the m PD78F0228 can select the internal memory capacities by using the memory size select register (ims). by setting ims, the memory mapping of the m PD78F0228 can be made the same as that of a mask rom model with different internal memory capacities. to make the memory map of the m PD78F0228 the same as that of a mask rom model, set ims as shown in table 15-2. ims is set by using an 8-bit memory manipulation instruction. the value of this register is set to cch by reset input. figure 15-1. memory size select register format ram2 ram1 ram0 selects internal high-speed ram capacity 1 1 0 1024 bytes others setting prohibited rom3 rom2 rom1 rom0 selects internal rom capacity 1 1 0 0 48k bytes 1 1 1 1 60k bytes others setting prohibited caution when using a mask rom model, do not set a value other than those shown in table 15-2 to ims. table 15-2. set value of memory size select register part number set value of ims m pd780226 cch m pd780228 cfh 7 ram2 6 ram1 5 ram0 4 0 3 rom3 2 rom2 1 rom1 0 rom0 symbol ims address fff0h at reset cch r/w r/w
177 chapter 15 m m m m m PD78F0228 15.2 internal expansion ram size select register the internal expansion ram size select register (ixs) specifies the internal expansion ram capacity. ixs is set by using an 8-bit memory manipulation instruction. the value of this register is set to 0ch by reset input. caution be sure to set 0bh to ixs in the initial settings of the program. because ixs is set to 0ch at reset, be sure to set the register to 0bh again after reset. figure 15-2. internal expansion ram size select register format ixs is not provided on the m pd780226 and 780228. however, the operation is not affected even if an instruction that writes data to ixs is executed on the m pd780226 and 780228. 0 0 0 ixram4 ixram3 ixram2 ixram1 ixram0 76543210 fff4h address 0ch at reset r/w r/w 01011 ixram4 ixram3 ixram2 ixram1 ixram0 512 bytes selects internal expansion ram capacity setting prohibited others ixs symbol
178 chapter 15 m m m m m PD78F0228 15.3 flash memory programming the flash memory can be written with the device mounted on the target system (on-board). to write the flash memory, connect a dedicated flash writer (flashpro ii: part number fl-pr2) to the host machine and target system. the flash memory can be also written on a flash memory writing adapter connected to the flashpro ii. remark flashpro ii is a product of naito densei machida mfg. co., ltd. 15.3.1 selecting communication mode the flash memory is written by using the flashpro ii and by means of serial communication. select one of the communication modes listed in table 15-3 to write the flash memory. to select a communication mode, use the format shown in figure 15-3. each communication mode is selected by the number of v p-p pulses shown in table 15-3. table 15-3. communication modes communication mode number of channels pin used number of v p-p pulses 3-wire serial i/o 1 sck/p20 0 so/p21 si/p22 pseudo 3-wire serial i/o note 1 p40 (serial clock i/o) 12 p41 (serial data output) p42 (serial data input) note execute serial transfer by controlling the ports by software. caution be sure to select a communication mode with the number of v p-p pulses shown in table 15-3. figure 15-3. communication mode select format v pp pulses flash memory writing mode v pp 10 v v dd v ss v dd v ss reset
179 chapter 15 m m m m m PD78F0228 15.3.2 function of flash memory programming by transmitting/receiving commands/data in the selected communication mode, operations of the flash memory such as writing are performed. table 15-14 lists the major functions of the flash memory programming. table 15-4. major functions of flash memory programming function description reset used to stop writing or detect communication synchronization batch verify compares all memory contents with input data batch erase erases all memory contents batch blank check checks erased status of entire memory high-speed write writes flash memory based on write start address and number of written data (number of bytes) successive write successively writes based on information input in high-speed write mode status used to check current operation mode and end of operation oscillation frequency setting inputs frequency information on oscillator erase time setting inputs erase time of memory silicon signature read outputs device name, memory capacity, and block information of device
180 chapter 15 m m m m m PD78F0228 15.3.3 connection of flashpro ii connection between the flashpro ii and m PD78F0228 differs depending on the selected communication mode. figures 15-4 and 15-5 show the connections in the respective mode. figure 15-4. connection of flashpro ii in 3-wire serial i/o mode figure 15-5. connection of flashpro ii in pseudo 3-wire serial i/o mode v pp v dd reset sck so si v pp v dd reset v ss flashpro ii PD78F0228 sck si so v ss m v pp v dd reset sck so si v ss v pp v dd reset p40 (serial clock) p42 (serial input) p41 (serial output) v ss flashpro ii PD78F0228 m
chapter 16 instruction set 181 chapter 16 instruction set the instruction set for the m pd780228 subseries is described in the following pages. for the details of operations and mnemonics (instruction codes) of each instruction, refer to 78k/0 series users manual: instructions (u12326e) .
chapter 16 instruction set 182 16.1 legend 16.1.1 operand identifiers and description methods operands are described in the operand column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more description methods, select one of them. alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and are described as they are. symbols have the following meaning. ? # : immediate data specification ? ! : absolute address specification ? $ : relative address specification ? [ ] : indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $ and [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. table 16-1. operand identifiers and description methods identifier description method r x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) rp ax (rp0), bc (rp1), de (rp2), hl (rp3) sfr special function register symbol note sfrp special function register symbols (16-bit manipulatable register even addresses only) note saddr fe20h to ff1fh immediate data or labels saddrp fe20h to ff1fh immediate data or labels (even addresses only) addr16 0000h to ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) addr11 0800h to 0fffh immediate data or labels addr5 0040h to 007fh immediate data or labels (even addresses only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label rbn rb0 to rb3 note ffd0h to ffdfh are not addressable. remark for special-function register symbols, refer to table 3-3 special function register list .
chapter 16 instruction set 183 16.1.2 description of operation column a : a register; 8-bit accumulator x : x register b : b register c : c register d : d register e : e register h : h register l : l register ax : ax register pair; 16-bit accumulator bc : bc register pair de : de register pair hl : hl register pair pc : program counter sp : stack pointer psw : program status word cy : carry flag ac : auxiliary carry flag z : zero flag rbs : register bank select flag ie : interrupt request enable flag nmis : non-maskable interrupt servicing flag ( ) : memory contents indicated by address or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register ? : logical product (and) | : logical sum (or) | : exclusive logical sum (exclusive or) : inverted data addr16 : 16-bit immediate data or label jdisp8 : signed 8-bit data (displacement value) 16.1.3 description of flag operation column (blank) : unchanged 0 : cleared to 0 1 : set to 1 x : set/cleared according to the result r : previously saved value is restored
chapter 16 instruction set 184 16.2 operation list instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy r, #byte 2 4 r byte saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 7 sfr byte a, r note 3 12 a r r, a note 3 12 r a a, saddr 2 4 5 a (saddr) saddr, a 2 4 5 (saddr) a a, sfr 2 5 a sfr sfr, a 2 5 sfr a a, !addr16 3 8 9 a (addr16) !addr16, a 3 8 9 (addr16) a mov psw, #byte 3 7 psw byte a, psw 2 5 a psw psw, a 2 5 psw a a, [de] 1 4 5 a (de) [de], a 1 4 5 (de) a a, [hl] 1 4 5 a (hl) [hl], a 1 4 5 (hl) a a, [hl+byte] 2 8 9 a (hl + byte) [hl+byte], a 2 8 9 (hl + byte) a a, [hl+b] 1 6 7 a (hl + b) [hl+b], a 1 6 7 (hl + b) a a, [hl+c] 1 6 7 a (hl + c) [hl+c], a 1 6 7 (hl + c) a a, r note 3 12 a r a, saddr 2 4 6 a (saddr) a, sfr 2 6 a sfr a, !addr16 3 8 10 a (addr16) xch a, [de] 1 4 6 a (de) a, [hl] 1 4 6 a (hl) a, [hl+byte] 2 8 10 a (hl + byte) a, [hl+b] 2 8 10 a (hl + b) a, [hl+c] 2 8 10 a (hl + c) notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except r = a remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 8-bit data transfer
chapter 16 instruction set 185 instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy rp, #word 3 6 rp word saddrp, #word 4 8 10 (saddrp) word sfrp, #word 4 10 sfrp word ax, saddrp 2 6 8 ax (saddrp) saddrp, ax 2 6 8 (saddrp) ax movw ax, sfrp 2 8 ax sfrp sfrp, ax 2 8 sfrp ax ax, rp note 3 1 4 ax rp rp, ax note 3 1 4 rp ax ax, !addr16 3 10 12 ax (addr16) !addr16, ax 3 10 12 (addr16) ax xchw ax, rp note 3 1 4 ax rp a, #byte 2 4 a, cy a + byte saddr, #byte 3 6 8 (saddr), cy (saddr) + byte a, r note 4 2 4 a, cy a + r r, a 2 4 r, cy r + a add a, saddr 2 4 5 a, cy a + (saddr) a, !addr16 3 8 9 a, cy a + (addr16) a, [hl] 1 4 5 a, cy a + (hl) a, [hl+byte] 2 8 9 a, cy a + (hl + byte) a, [hl+b] 2 8 9 a, cy a + (hl + b) a, [hl+c] 2 8 9 a, cy a + (hl + c) a, #byte 2 4 a, cy a + byte + cy saddr, #byte 3 6 8 (saddr), cy (saddr) + byte + cy a, r note 4 2 4 a, cy a + r + cy r, a 2 4 r, cy r + a + cy addc a, saddr 2 4 5 a, cy a + (saddr) + cy a, !addr16 3 8 9 a, cy a + (addr16) + cy a, [hl] 1 4 5 a, cy a + (hl) + cy a, [hl+byte] 2 8 9 a, cy a + (hl + byte) + cy a, [hl+b] 2 8 9 a, cy a + (hl + b) + cy a, [hl+c] 2 8 9 a, cy a + (hl + c) + cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de or hl 4. except r = a remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 16-bit data transfer 8-bit operation
chapter 16 instruction set 186 instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy a, #byte 2 4 a, cy a C byte saddr, #byte 3 6 8 (saddr), cy (saddr) C byte a, r note 3 2 4 a, cy a C r r, a 2 4 r, cy r C a sub a, saddr 2 4 5 a, cy a C (saddr) a, !addr16 3 8 9 a, cy a C (addr16) a, [hl] 1 4 5 a, cy a C (hl) a, [hl+byte] 2 8 9 a, cy a C (hl + byte) a, [hl+b] 2 8 9 a, cy a C (hl + b) a, [hl+c] 2 8 9 a, cy a C (hl + c) a, #byte 2 4 a, cy a C byte C cy saddr, #byte 3 6 8 (saddr), cy (saddr) C byte C cy a, r note 3 2 4 a, cy a C r C cy r, a 2 4 r, cy r C a C cy subc a, saddr 2 4 5 a, cy a C (saddr) C cy a, !addr16 3 8 9 a, cy a C (addr16) C cy a, [hl] 1 4 5 a, cy a C (hl) C cy a, [hl+byte] 2 8 9 a, cy a C (hl + byte) C cy a, [hl+b] 2 8 9 a, cy a C (hl + b) C cy a, [hl+c] 2 8 9 a, cy a C (hl + c) C cy a, #byte 2 4 a a ? byte saddr, #byte 3 6 8 (saddr) (saddr) ? byte a, r note 3 24 a a ? r r, a 2 4 r r ? a and a, saddr 2 4 5 a a ? (saddr) a, !addr16 3 8 9 a a ? (addr16) a, [hl] 1 4 5 a a ? (hl) a, [hl+byte] 2 8 9 a a ? (hl + byte) a, [hl+b] 2 8 9 a a ? (hl + b) a, [hl+c] 2 8 9 a a ? (hl + c) notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except r = a remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 8-bit operation
chapter 16 instruction set 187 instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy a, #byte 2 4 a a | byte saddr, #byte 3 6 8 (saddr) (saddr) | byte a, r note 3 24 a a | r r, a 2 4 r r | a or a, saddr 2 4 5 a a | (saddr) a, !addr16 3 8 9 a a | (addr16) a, [hl] 1 4 5 a a | (hl) a, [hl+byte] 2 8 9 a a | (hl + byte) a, [hl+b] 2 8 9 a a | (hl + b) a, [hl+c] 2 8 9 a a | (hl + c) a, #byte 2 4 a a | byte saddr, #byte 3 6 8 (saddr) (saddr) | byte a, r note 3 24 a a | r r, a 2 4 r r | a xor a, saddr 2 4 5 a a | (saddr) a, !addr16 3 8 9 a a | (addr16) a, [hl] 1 4 5 a a | (hl) a, [hl+byte] 2 8 9 a a | (hl + byte) a, [hl+b] 2 8 9 a a | (hl + b) a, [hl+c] 2 8 9 a a | (hl + c) a, #byte 2 4 a C byte saddr, #byte 3 6 8 (saddr) C byte a, r note 3 24 a C r r, a 2 4 r C a cmp a, saddr 2 4 5 a C (saddr) a, !addr16 3 8 9 a C (addr16) a, [hl] 1 4 5 a C (hl) a, [hl+byte] 2 8 9 a C (hl + byte) a, [hl+b] 2 8 9 a C (hl + b) a, [hl+c] 2 8 9 a C (hl + c) notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except r = a remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 8-bit operation
chapter 16 instruction set 188 instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy addw ax, #word 3 6 ax, cy ax + word subw ax, #word 3 6 ax, cy ax C word cmpw ax, #word 3 6 ax C word mulu x 2 16 ax a x divuw c 2 25 ax (quotient), c (remainder) ax c inc r12r r + 1 saddr 2 4 6 (saddr) (saddr) + 1 dec r12r r C 1 saddr 2 4 6 (saddr) (saddr) C 1 incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp C 1 ror a, 1 1 2 (cy, a 7 a 0 , a mC1 a m ) 1 rol a, 1 1 2 (cy, a 0 a 7 , a m+1 a m ) 1 rorc a, 1 1 2 (cy a 0 , a 7 cy, a mC1 a m ) 1 rotation rolc a, 1 1 2 (cy a 7 , a 0 cy, a m+1 a m ) 1 ror4 [hl} 2 10 12 a 3C0 (hl) 3C0 , (hl) 7C4 a 3C0 , (hl) 3C0 (hl) 7C4 rol4 [hl] 2 10 12 a 3C0 (hl) 7C4 , (hl) 3C0 a 3C0 , (hl) 7C4 (hl) 3C0 adjba 24 decimal adjust accumulator after addition adjbs 24 decimal adjust accumulator after subtract cy, saddr.bit 3 6 7 cy (saddr.bit) cy, sfr.bit 3 7 cy sfr.bit cy, a.bit 2 4 cy a.bit cy, psw.bit 3 7 cy psw.bit mov1 cy, [hl].bit 2 6 7 cy (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) cy sfr.bit, cy 3 8 sfr.bit cy a.bit, cy 2 4 a.bit cy psw.bit, cy 3 8 psw.bit cy [hl].bit, cy 2 6 8 (hl).bit cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). increase/ decrease multiply/ divide 16-bit operation bcd correction bit manipulation
chapter 16 instruction set 189 instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy cy, saddr.bit 3 6 7 cy cy ? (saddr.bit) cy, sfr.bit 3 7 cy cy ? sfr.bit and1 cy, a.bit 2 4 cy cy ? a.bit cy, psw.bit 3 7 cy cy ? psw.bit cy, [hl].bit 2 6 7 cy cy ? (hl).bit cy, saddr.bit 3 6 7 cy cy | (saddr.bit) cy, sfr.bit 3 7 cy cy | sfr.bit or1 cy, a.bit 2 4 cy cy | a.bit cy, psw.bit 3 7 cy cy | psw.bit cy, [hl].bit 2 6 7 cy cy | (hl).bit cy, saddr.bit 3 6 7 cy cy | (saddr.bit) cy, sfr.bit 3 7 cy cy | sfr.bit xor1 cy, a.bit 2 4 cy cy | a.bit cy, psw.bit 3 7 cy cy | psw.bit cy, [hl].bit 2 6 7 cy cy | (hl).bit saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 8 sfr.bit 1 set1 a.bit 2 4 a.bit 1 psw.bit 2 6 psw.bit 1 [hl].bit 2 6 8 (hl).bit 1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 8 sfr.bit 0 clr1 a.bit 2 4 a.bit 0 psw.bit 2 6 psw.bit 0 [hl].bit 2 6 8 (hl).bit 0 set1 cy 1 2 cy 11 clr1 cy 1 2 cy 00 not1 cy 1 2 cy cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). bit manipulation
chapter 16 instruction set 190 instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy (sp C 1) (pc + 3) h , call !addr16 3 7 (sp C 2) (pc + 3) l , pc addr16, sp sp C 2 (sp C 1) (pc + 2) h , callf !addr11 2 5 (sp C 2) (pc + 2) l , pc 15C11 00001, pc 10C0 addr11, sp sp C 2 (sp C 1) (pc + 1) h , (sp C 2) (pc +1 ) l , callt [addr5] 1 6 pc h (00000000, addr5 + 1), pc l (00000000, addr5) sp sp C 2 (sp C 1) psw, (sp C 2) (pc + 1) h , brk 1 6 (sp C 3) (pc + 1) l , pc h (003fh), pc l (003eh), sp sp C 3, ie 0 ret 16 pc h (sp + 1), pc l (sp), sp sp + 2 pc h (sp + 1), pc l (sp), reti 1 6 psw (sp + 2), sp sp + 3, r r r nmis 0 retb 16 pc h (sp + 1), pc l (sp), rrr psw (sp + 2), sp sp + 3 psw 1 2 (sp C 1) psw, sp sp C 1 push rp 1 4 (sp C 1) rp h , (sp C 2) rp l , sp sp C 2 psw 1 2 psw (sp), sp sp + 1 r r r pop rp 1 4 rp h (sp + 1), rp l (sp), sp sp + 2 sp, #word 4 10 sp word movw sp, ax 2 8 sp ax ax, sp 2 8 ax sp !addr16 3 6 pc addr16 br $addr16 2 6 pc pc + 2 jdisp8 ax 2 8 pc h a, pc l x bc $addr16 2 6 pc pc + 2 jdisp8 if cy = 1 bnc $addr16 2 6 pc pc + 2 jdisp8 if cy = 0 bz $addr16 2 6 pc pc + 2 jdisp8 if z = 1 bnz $addr16 2 6 pc pc + 2 jdisp8 if z = 0 notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). conditional branch unconditional branch stack manipulation call return
chapter 16 instruction set 191 instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy saddr.bit, $addr16 3 8 9 pc pc + 3 + jdisp8 if(saddr.bit) = 1 sfr.bit, $addr16 4 11 pc pc + 4 + jdisp8 if sfr.bit = 1 bt a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 9 pc pc + 3 + jdisp8 if psw.bit = 1 [hl].bit, $addr16 3 10 11 pc pc + 3 + jdisp8 if (hl).bit = 1 saddr.bit, $addr16 4 10 11 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 11 pc pc + 4 + jdisp8 if sfr.bit = 0 bf a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 11 pc pc + 4 + jdisp8 if psw.bit = 0 [hl].bit, $addr16 3 10 11 pc pc + 3 + jdisp8 if (hl).bit = 0 pc pc + 4 + jdisp8 saddr.bit, $addr16 4 10 12 if(saddr.bit) = 1 then reset (saddr.bit) sfr.bit, $addr16 4 12 pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit btclr a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr16 4 12 pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit [hl].bit.$addr16 3 10 12 pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit b, $addr16 2 6 b b C 1, then pc pc + 2 + jdisp8 if b ? 0 dbnz c, $addr16 2 6 c c C 1, then pc pc + 2 + jdisp8 if c ? 0 saddr, $addr16 3 8 10 (saddr) (saddr) C1 , then pc pc + 3 + jdisp8 if (saddr) ? 0 sel rbn 2 4 rbs1, 0 n nop 1 2 no operation ei 2 6 ie 1 (enable interrupt) di 2 6 ie 0 (disable interrupt) halt 2 6 set halt mode stop 2 6 set stop mode notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). conditional branch cpu control
chapter 16 instruction set 192 16.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz
chapter 16 instruction set 193 [hl+byte] #byte a r note sfr saddr !addr16 psw [de] [hl] [hl+b] $addr16 1 none [hl+c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl+byte] mov [hl+b] [hl+c] x mulu c divuw note except r = a second operand first operand
chapter 16 instruction set 194 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw #word ax rp note sfrp saddrp !addr16 sp none ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1 first operand second operand first operand second operand
chapter 16 instruction set 195 (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz ax !addr16 !addr11 [addr5] $addr16 basic instruction br call callf callt br br bc bnc bz bnz compound instruciton bt bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop first operand second operand
chapter 16 instruction set 196 [memo]
appendix a differences between m m m m m pd78044h, 780228, and 780208 subseries 197 appendix a differences between m m m m m pd78044h, 780228, and 780208 subseries table a-1 shows the major differences between the m pd78044h, 780228, and 780208 subseries. table a-1. major differences between m m m m m pd78044h, 780226, and 780208 subseries part number m pd78044h subseries m pd780228 subseries m pd780208 subseries item prom or flash memory model m pd78p048b m PD78F0228 m pd78p0208 (prom) (flash memory) (prom) supply voltage v dd = 2.7 to 5.5 v v dd = 4.5 to 5.5 v v dd = 2.7 to 5.5 v internal rom size m pd78044h: 32k bytes m pd780226: 48k bytes m pd780204: 32k bytes m pd78045h: 40k bytes m pd780228: 60k bytes m pd780205: 40k bytes m pd78046h: 48k bytes m PD78F0228: 60k bytes m pd780206: 48k bytes m pd780p048b: 60k bytes m pd780208: 60k bytes m pd78p0208: 60k bytes internal expansion ram size m pd78p048b only: 1024 bytes 512 bytes m pd780206, 780208, and 78p0208 only: 1024 bytes internal buffer ram size m pd78p048b only: 64 bytes none 64 bytes fip display ram size 48 bytes 96 bytes 80 bytes cpu clock main system clock or main system clock only main system clock or subsystem clock selectable subsystem clock selectable i/o port 68 pins 72 pins 74 pins total of fip display output pins 34 pins 48 pins 53 pins serial interface 1 channel 2 channels timer 16-bit timer/event counter 8-bit remote control timer 16-bit timer/event counter : 1 channel : 1 channel : 1 channel 8-bit timer/event counter 8-bit pwm timer: 2 channels 8-bit timer/event counter : 2 channels watchdog timer : 1 channel : 2 channels watch timer : 1 channel watch timer : 1 channel watchdog timer: 1 channel watchdog timer: 1 channel clock output provided none provided buzzer output provided none provided vectored interrupt internal 10 8 11 source external 4 4 4 test input provided none provided package 80-pin plastic qfp 100-pin plastic qfp 100-pin plastic qfp (14 20 mm) (14 20 mm) (14 20 mm) 80-pin ceramic wqfn 100-pin ceramic wqfn ( m pd78p048b only) ( m pd78p0208 only) electrical characteristics and refer to individual data sheet. recommended soldering conditions remark in addition to the above items, the organization of the development tools also differ between the above subseries (especially between the prom model and flash memory model). for details, refer to the users manual of each subseries.
appendix a differences between m m m m m pd78044h, 780228, and 780208 subseries 198 [memo]
appendix b development tools 199 appendix b development tools the following development tools are available for the development of systems which employ the m pd780228 subseries. figure b-1 shows the development tools.
appendix b development tools 200 figure b-1. development tools embedded software ?real-time os and os ?fuzzy inference development support system host machine (pc or ews) interface adapter flash writer flash memory writing adapter flash memory containing version in-circuit emulator probe board emulation probe conversion socket target system flash memory programming preference language processing software ?assembler package ?c compiler package ?c library source file ?system simulator ?integrated debugger ?device file i/o board
appendix b development tools 201 b.1 language processing software ra78k/0 this is a program to convert a program written in mnemonics into an object code executable with a assembler package microcontroller. further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. used in combination with optional device file (df780228). part number: m sxxxxra78k0 cc78k/0 this is a program to convert a program written in c language into an object code executable with c compiler package a microcontroller. used in combination with optional assembler package (ra78k/0) and device file (df780228). part number: m sxxxxcc78k0 df780228 note 1, 2 this is a file containning the information inherent to the device. device file used in combination with optional ra78k/0, cc78k/0, sm78k0, or id78k0. part number: m sxxxxdf780228 cc78k/0-l a function source program configurating object library included in c compiler (cc78k/0). c library source file necessary for changing object library included in cc78k/0 according to customers specifications. part number: m sxxxxcc78k0-l notes 1. the df780228 can be used for any of the ra78k/0, cc78k/0, sm78k0, and id78k0 products. 2. under development remark xxxx in the part number differs depending on the host machine and os used. m sxxxxra78k0 m sxxxxcc78k0 m sxxxxdf780228 m sxxxxcc78k0-l xxxx host machine os distribution medium 5a13 pc-9800 series ms-dos 3.5-inch 2hd 5a10 (ver.3.30 to ver.6.2 note ) 5-inch 2hd 7b13 ibm pc/at and refer to b.4 3.5-inch 2hc 7b10 compatible machines 5-inch 2hc 3h15 hp9000 series 300 tm hp-ux tm (rel.7.05b) cartridge tape (qic-24) 3p16 hp9000 series 700 tm hp-ux (rel.9.01) digital audio tape (dat) 3k15 sparcstation tm sunos tm (rel.4.1.1) cartridge tape 3m15 ews4800 series (risc) ews-ux/v (rel.4.0) (qic-24) note although ms-dos ver. 5.0 and above have a task swap function, this function cannot be used with this software.
appendix b development tools 202 b.2 flash memory writing tools flashpro ii flash writer dedicated to microcontroller with flash memory. (part number: fl-pr2) this is a product of naito densei machida mfg. co., ltd. flash writer fa-100gf flash memory writing adapter for m pd780228 subseries and is connected to flashpro ii. flash memory writing adapter this adapter is for a 100-pin plastic qfp (gf-3ba type). this is a product of naito densei machida mfg. co., ltd.
appendix b development tools 203 b.3 debugging tools b.3.1 hardware ie78001-r-a-sl note this in-circuit emulator is used to debug the hardware and software when an application system in-circuit emulator using the 78k/0 series is developed. it supports the integrated debugger (id78k0). this emulator is used with an emulation probe, and an interface adapter to connect the host machine. ie-70000-98-if-b adapter necessary for using the pc-9800 series (excluding the notebook type) as the host machine interface adapter of the ie-78001-r-a. ie-70000-98n-f adapter and cable necessary for using a pc-9800 series notebook type computer as the host machine interface adapter of the ie-78001-r-a. this adapter cannot be connected unless the connector of the expansion bus of the notebook type computer is of 110-pin type. ie-70000-pc-if-b adapter necessary for using an ibm pc/at or compatible machine as the host machine of the ie- interface adapter. 78001-r-a. ie-78k0-sl-p01 note this board is used to emulate device-specific hardware. it is used with an in-circuit emulator and i/o board probe board. ie-780228-sl-em4 note this board is used to set mask option and converts pin connector. probe board ep-100gf-sl this probe connects an in-circuit emulator and the target system. it is for a 100-pin plastic qfp (gf- emulation probe 3ba type). a 100-pin conversion socket, nqpack100rb, and a conversion adapter, yqpack100rb, which facilitates development of the target system, are also supplied. nqpack100rb this conversion socket is used to connect the board of the target system that is designed to mount conversion socket a 100-pin plastic qfp (gf-3ba type), and the ep100gf-sl. to connect the ep-100gf-sl, this socket is used with yqpack100rb. instead of connecting ep-100gf-sl, a device can be mounted. yqpack100rb this is a conversion adapter used to connect the nqpack100rb and ep-100gf-sl. conversion adapter hqpack100rb this is a lid used when a device is mounted to the nqpack100rb. note under development remarks 1. nqpack100rb, yqpack100rb, and hqpack100rb are products of tokyo eletech corp. (03- 5295-1661). consult nec distributor when purchasing these products. 2. nqpack100rb, yqpack100rb, and hqpack100rb are available in one unit.
appendix b development tools 204 b.3.2 software (1/2) sm78k0 debugs program at c source level or assembler level while simulating operation of target system system simulator on host machine. sm78k0 runs on windows. by using the sm78k0, the logic and performance of an application can be verified independently of hardware development even when the in-circuit emulator is not used. this enhances development efficiency and improves software quality. used in combination with optional device file (df780228). part number : m sxxxxsm78k0 remark xxxx in the part number differs depending on the host machine and os used. m sxxxxsm78k0 xxxx host machine os distribution medium aa13 pc-9800 series ms-dos 3.5-inch 2hd (ver.3.30 to ver.6.2 note ) + windows (ver.3.0 to ver.3.1) ab13 ibm pc/at and refer to b.4 3.5-inch 2hc compatible machines (windows japanese version) bb13 ibm pc/at and compatible machines (windows english version) note although ms-dos ver. 5.0 and above have a task swap function, this function cannot be used with this software.
appendix b development tools 205 b.3.2 software (2/2) id78k0 the id78k0 is a control program to debug the 78k/0 series. integrated debugger the id78k0 uses windows on personal computers and osf/motif? on ews as graphical interface, and presents the appearance and operatability conforming to these platforms. the id78k0 has enhanced debugging function supporting c language, and the trace result can be displayed by using the window integration function that interlocks source program, disassemble display, and memory display to the trace result. in addition, debugging efficiency for programs using real time os can be enhanced by incorporating extension modules such as task debugger and system performance analyzer. used in combination with optional device file (df780228). part number : m sxxxxid78k0 remark xxxx in the part number differs depending on the host machine and os used. m sxxxxid78k0 xxxx host machine os distribution medium aa13 pc-9800 series ms-dos 3.5-inch 2hd (ver.3.30 to ver.6.2 note ) + windows (ver.3.1) ab13 ibm pc/at and their refer to b.4 3.5-inch 2hc compatible machines (windows japanese version) bb13 ibm pc/at and their 3.5-inch 2hc compatible machines ( windows english version) 3p16 hp9000 series 700 hp-ux (rel.9.01) digital audio tape (dat) 3k15 sparcstation sunos (rel.4.1.1) cartridge tape (qic-24) 3k13 3.5-inch 2hc 3r16 news tm (risc) news-os tm (6.1x) 1/4-inch cgmt 3r13 3.5-inch 2hc 3m15 ews4800 series (risc) ews-ux/v (rel.4.0) cartridge tape (qic-24) note although ms-dos ver. 5.0 and above have a task swap function, this function cannot be used with this software.
appendix b development tools 206 b.4 os for ibm pc the following oss for the ibm pc are supported. to operate sm78k0, id78k/0, and fe9200 (refer to c.2 fuzzy inference development support system ), windows (ver. 3.0 to ver. 3.1) is necessary. os version pc dos ver. 5.02 to ver. 6.3 j6.1/v note to j6.3/v note ibm dos tm j5.02/v note ms-dos ver. 5.0 to ver. 6.22 5.0/v note to 6.2/v note note only english mode is supported. caution although ms-dos ver. 5.0 and above have a task swap function, this function cannot be used with this software. C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
appendix b development tools 207 package drawings of nqpack100rb, hqpack100rb, and yqpack100rb figure b-2. nqpack100rb (target-connected side) package drawings (reference) remark manufactured by tokyo eletech corp. item millimeters inches b 0.5 0.020 c 0.5 0.020 a 22.75 0.896 d 4- 2.0 4- 0.079 h 3.7 0.146 i 3.9 0.154 j 0.2 0.008 e 1.8 0.071 f 9.45 g 1.85 0.073 0.372 item millimeters inches b 14.25 0.561 c 0.65x19=12.35 0.026x0.748=0.486 a 21.75 0.856 d h 17.4 0.685 i 21.75 0.856 j 0.65x29=18.85 0.026x1.142=0.742 e 7.0 0.276 f 20.75 0.817 k 23.9 0.941 l 0.65 0.026 m q 3-r 1.5 3-r 0.059 r 17.15 0.675 s 10.0 0.394 n 6.0 0.236 o 3- 1.0 p c 1.5 c 0.059 3- 0.039 w 16.25 0.640 x 0.5 0.020 y 0.5 0.020 t 12.0 0.472 u 23.65 v 15.25 0.600 0.931 z 21.75 0.856 0.65 0.4 0.026 0.016 g 28.25 1.112 k 1.2 0.047 n 0.5 0.020 o 0.25 0.010 p 0.5 0.020 l 15.25 m 16.25 0.640 0.600 q 6.95 0.274 ff f f z j g q f v r a h l p n p q l protrusion height d e slit width b c d m k n o f e i s c a y w x m o i h g k j t u b nqpack100rb-g1e
appendix b development tools 208 figure b-3. hqpack100rb (lid for device mounted) package drawings (reference) remark manufactured by tokyo eletech corp. item millimeters inches b 1.6 0.063 c 0.25 0.010 a 2.25 0.089 d 16.57 0.652 h 2.3 0.091 i 1.2 0.047 j 3.1 0.122 e 17.57 0.692 f 0.5 g 3.9 0.154 0.020 item millimeters inches b c 0.65 0.026 a 17.4 0.685 d h i 30.25 1.191 j 0.65 0.026 e 23.75 0.935 f 7.0 0.276 k 3- 1.0 3- 0.039 l c 2.0 c 0.079 m q 23.07 0.908 r 0.5 0.020 s 0.5 0.020 n 4- 2.2 4- 0.087 o 14.1 p 24.07 0.948 0.555 w 0.5 0.020 x 20.1 0.791 y 0.2 0.008 t 16.57 0.652 u 17.57 v 0.5 0.020 0.692 z c 1.5 c 0.059 6.0 3-r 2.5 0.236 3-r 0.098 g 0.65x29=18.85 0.026x1.142=0.742 k 7.4 0.291 0.65x19=12.35 23.9 0.026x0.748=0.486 0.941 f f f f x q p o t u a b f g h i e k f d e c d c l n j m k z y s v r w j i h g b a hqpack100rb-g0e
appendix b development tools 209 figure b-4. yqpack100rb (probe side) package drawings (reference) remark manufactured by tokyo eletech corp. item millimeters inches b c 0.65 0.026 a 17.4 0.685 d h i 10.35 0.407 j 12.75 0.502 e 16.85 0.663 f 19.25 0.758 k 15.15 0.596 l 17.55 0.691 m q 0.65 0.026 r 7.0 0.276 s 0.25 0.010 n 0.65x29=18.85 0.026x1.142=0.742 o 23.9 p 30.25 1.191 0.941 w 4- 2.2 4- 0.087 x 14.1 0.555 y 21.25 0.837 t 3- 1.0 3- 0.039 u c 2.0 v 3-r 2.5 3-r 0.098 c 0.079 z 22.05 0.868 6.0 23.75 0.236 0.935 g 21.65 0.852 0.65x19=12.35 24.05 0.026x0.748=0.486 0.947 item millimeters inches b c 14.75 0.748 a 0.4 0.685 d h i c 1.5 c 0.059 j 0.3 0.012 e 0.4 0.016 f 0.4 0.016 k 0.25x0.3 0.010x0.012 l 9.0 0.354 m q 0.25 0.010 r 14.75 0.581 s 15.55 0.612 n 3.1 0.122 o 3.7 p 2.5 0.098 0.146 w 2.3 0.091 x 1.2 0.047 t 0.4 0.016 u 7.4 v 3.9 0.154 0.291 15.55 2.2 0.486 0.087 g 20.1 0.791 0.4 0.2 0.026 0.008 f f f f r n o p e f g h i j k l m v w a b d c u s q t z x y g h i b a e c d f k j p n m o l q r s t u x w v yqpack100rb-g0e
appendix b development tools 210 [memo]
appendix c embedded software 211 appendix c embedded software for efficient program development and maintenance of the m pd780228 subseries, the following embedded software products are available.
appendix c embedded software 212 c.1 real-time os (1/2) rx78k/0 rx78k/0 is a real-time os which is based on the m itron specification. real-time os supplied with the rx78k/0 nucleus and a tool to prepare multiple information tables (configurator). used in combination with optional assembler package (ra78k/0) and device file (df780228). part number: m sxxxxrx78013- caution when purchasing the rx78k/0, fill in the purchase application form in advance, and sign the user agreement. remark xxxx and in the part number differs depending on host machine and os, etc. m sxxxxrx78013- product outline maximum number for use in mass production 001 evaluation object do not use for mass-produced product. 100k mass production object 100,000 001m 1,000,000 010m 10,000,000 s01 source program source program of mass production object xxxx host machine os distribution medium 5a13 pc-9800 series ms-dos 3.5-inch 2hd 5a10 (ver. 3.30 to ver.6.2 note ) 5-inch 2hd 7b13 ibm pc/at and their refer to b.4 3.5-inch 2hc 7b10 compatible machines 5-inch 2hc 3h15 hp9000 series 300 hp-ux (rel.7.05b) cartridge tape (qic-24) 3p16 hp9000 series 700 hp-ux (rel.9.01) digital audio tape (dat) 3k15 sparcstation sunos (rel.4.1.1) cartridge tape 3m15 ews4800 series ews-ux/v (rel.4.0) (qic-24) (risc) note although ms-dos ver. 5.0 and above have a task swap function, this function cannot be used with this software.
appendix c embedded software 213 c.1 real-time os (2/2) mx78k0 m itron-specification subset os. nucleus of mx78k0 is supplied. os this os performs task management, event management, and time management. it controls the task execution sequence for task management and selects the task to be executed next. part number: m sxxxxmx78k0- remark xxxx and in the part number differs depending on the host machine and os, etc. m sxxxxmx78k0- product outline note 001 evaluation object use for trial product. xx mass production object use for mass-produced product. s01 source program can be purchased only when object for mass- produced product is purchased xxxx host machine os distribution medium 5a13 pc-9800 series ms-dos 3.5-inch 2hd 5a10 (ver. 3.30 to ver. 6.2 note ) 5-inch 2hd 7b13 ibm pc/at and their refer to b.4 3.5-inch 2hc 7b10 compatible machines 5-inch 2hc 3h15 hp9000 series 300 hp-ux (rel.7.05b) cartridge tape (qic-24) 3p16 hp9000 series 700 hp-ux (rel.9.01) digital audio tape (dat) 3k15 sparcstation sunos (rel.4.1.1) cartridge tape 3m15 ews4800 series ews-ux/v (rel.4.0) (qic-24) (risc) note although ms-dos ver. 5.0 and above have a task swap function, this function cannot be used with this software.
appendix c embedded software 214 c.2 fuzzy inference development support system fe9000/fe9200 program supporting input of fuzzy knowledge data (fuzzy rule and membership function), editing fuzzy knowledge data (edit), and evaluation (simulation). preparation tool fe9200 operations on windows. part number (product name): m sxxxxfe9000 (pc-9800 series) m sxxxxfe9200 (ibm pc/at and compatible machines) ft9080/ft9085 program converting fuzzy knowledge data obtained by using fuzzy knowledge data preparation translator tool to the assembler source program for the ra78k/0. part number (product name): m sxxxxft9080 (pc-9800 series) m sxxxxft9085 (ibm pc/at and compatible machines) fi78k0 program executing fuzzy inference. fuzzy inference is executed by linking fuzzy knowledge data fuzzy inference module converted by translator. part number (product name): m sxxxxfi78k0 (pc-9800 series, ibm pc/at and compatible machines) fd78k0 support software evaluating and adjusting fuzzy knowledge data at hardware level by using fuzzy inference debugger in-circuit emulator. part number (product name): m sxxxxfd78k0 (pc-9800 series, ibm pc/at and compatible machines) remark xxxx in the part number differs depending on the host machine and os. m sxxxxfe9000 m sxxxxft9080 m sxxxxfi78k0 m sxxxxfd78k0 xxxx host machine os distribution medium 5a13 pc-9800 series ms-dos 3.5-inch 2hd 5a10 (ver. 3.30 to ver. 6.2 note ) 5-inch 2hd note although ms-dos ver. 5.0 and above have a task swap function, this function cannot be used with this software. m sxxxxfe9200 m sxxxxft9085 m sxxxxfi78k0 m sxxxxfd78k0 xxxx host machine os distribution medium 7b13 ibm pc/at and refer to b.4 3.5-inch 2hc 7b10 compatible machines 5-inch 2hc
appendix d register index 215 appendix d register index d.1 register index [a] adcrh0 : a/d conversion result register ... 110 adm : a/d converter mode register ... 112 ad0s : a/d converter input select register ... 113 [c] cr10 : 8-bit compare register 10 ... 79 cr11 : 8-bit capture register 11 ... 79 cr50 : 8-bit compare register 50 ... 85 cr51 : 8-bit compare register 51 ... 85 csim3 : serial operating mode register 3 ... 123-125 [d] dspm0 : display mode register 0 ... 129 dspm1 : display mode register 1 ... 131 dspm2 : display mode register 2 ... 132 [e] egn : external interrupt falling edge enable register ... 151 egp : external interrupt rising edge enable register ... 151 [ i ] if0h : interrupt request flag register 0h ... 148 if0l : interrupt request flag register 0l ... 148 ims : internal memory size select register ... 176 ixs : internal expansion ram size select register ... 177 [m] mk0h : interrupt mask flag register 0h ... 149 mk0l : interrupt mask flag register 0l ... 149 [o] osts : oscillation stabilization time select register ... 103 [p] p0 : port 0 ... 51 p1 : port 1 ... 53 p2 : port 2 ... 54 p4 : port 4 ... 55 p5 : port 5 ... 56 p6 : port 6 ... 58 p7 : port 7 ... 59
appendix d register index 216 p8 : port 8 ... 60 p9 : port 9 ... 61 p10 : port 10 ... 62 plr7 : port read 7 ... 59 plr8 : port read 8 ... 60 plr9 : port read 9 ... 61 pcc : processor clock control register ... 70 pm0 : port mode register 0 ... 64 pm2 : port mode register 2 ... 64 pm4 : port mode register 4 ... 64 pm5 : port mode register 5 ... 64 pm6 : port mode register 6 ... 64 pr0h : priority specify flag register 0h ... 150 pr0l : priority specify flag register 0l ... 150 psw : program status word ... 28, 152 pu0 : pull-up resistor option register 0 ... 65 pu2 : pull-up resistor option register 2 ... 65 pu4 : pull-up resistor option register 4 ... 65 [s] sio3 : serial i/o shift register 1 ... 122 [t] tcl50 : timer clock select register 50 ... 86 tcl51 : timer clock select register 51 ... 86 tm50 : 8-bit counter 50 ... 85 tm51 : 8-bit counter 51 ... 85 tmc1 : timer mode control register 1 ... 79 tmc50 : 8-bit timer mode control register 50 ... 87 tmc51 : 8-bit timer mode control register 51 ... 87 [w] wdcs : watchdog timer clock select register ... 104 wdtm : watchdog timer mode register ... 105
appendix e revision history 217 appendix e revision history this table shows the revision history of this manual. the column under the heading chapter indicates the chapter of the preceding edition in which a revision has been made. edition major revision from previous edition chapter 2nd edition change of m pd780226 and 780228 from under development to throughout developed change of i/o circuit types of ports 7, 8, 9, and 10 of mask rom chapter 2 pin functions model as follows: ports 7, 8, and 9: type 15-d to type 15-f port 10 : type 14-d to type 14-f addition of internal expansion ram size select register (ixs) chapter 3 cpu architecture chapter 14 reset function chapter 15 m PD78F0228 correction of block diagrams of ports 7, 8, 9, and 10 chapter 4 port functions change of notes on inputting external clock chapter 5 clock generator change of count clock value by setting of tlc2 and tcl1 in chapter 6 8-bit remote figure 6-2 timer mode control register 1 format control timer change of oscillation stabilization time by setting of osts2-osts0 chapter 8 watchdog timer in format of oscillation stabilization time select register chapter 13 standby function change of setting of fout5-fout0, and addition of notes on fip chapter 11 fip controller/ output pins driver addition of 11.7 calculation of total power dissipation change of product name of dedicated flash writer as follows: chapter 15 m PD78F0228 flashpro to falshpro ii (part no.: fl-pr2) appendix b development tools addition of appendix a differences between m m m m m pd78044h, appendix a differences 780228, and 780208 subseries between m pd78044h, 780228, and 780208 subseries change of hardware for debugging tools as follows: appendix b development tools change of ie-780000-sl to ie-78001-r-a deletion of ie-78k0-sl-em (cpu core board) change of ep-100gf-sl from under development to developed deletion of upgrading your in-circuit emulator to emulator for 78k/0 series
appendix e revision history 218 [memo]
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